Katsuzo Kaminishi

Growth of Single Domain GaAs Layer on (100)-Oriented Si Substrate by MOCVD

Single domain GaAs layers with satisfactory morphology were grown on (100)-oriented Si substrates by heat treatment of the substrates at above 900°C and subsecquent two-step growth at low temperatures of 450°C or below and by conventional growth temperatures. The grown GaAs layers showed a high mobility of 5200 cm2V-1s-1 at room temperature with a carrier density of 1×1016 cm-3.

Growth of GaAs on Si by MOVCD

Abstract GaAs layers with a mirror surface were grown on (100)-oriented Si substrate by MOVCD. The combination of thin GaAs layers grown at low temperatures and GaAs/GaAlAs alternating layers at conventional growth temperatures were found to be effective as a buffer layer. The top GaAs layer showed a relatively high PL intensity although the peak shifted to 834 nm due to the tensile stress arising from the difference in thermal expansion coefficient between GaAs and Si. The growth conditions and the construction of the buffer layer to enable the growth of a good GaAs layer were studied.

Growth of high quality GaAs layers on Si substrates by MOCVD

Abstract High quality GaAs layers were grown on Si(100) wafers by heat treatment of the substrates at high temperatures and a subsequent two-step growth sequence at low temperature and then at the conventional growth temperature. The grown layers showed a high quality, i.e., a single domain structure, a mirror-like surface, high electron mobility, fairly high photoluminescence intensity and low etch pit density. Cross-sectional TEM observation showed that most of the misfit dislocations were confined in the narrow region near the GaAs/Si interface. The growth of GaAs on Si substrates with spherical surfaces showed that a small offset angle from (100) was necessary to grow a single domain GaAs layer. FETs and LEDs fabricated on the grown layers showed nearly the same characteristics as those of the devices on GaAs wafers.

Growth of Single Domain GaAs on 2-inch Si(100) Substrate by Molecular Beam Epitaxy

Good surface morphological single domain GaAs films were successfully grown on a whole area of 2-inch Si(100) substrates by molecular beam epitaxy (MBE). Si substrates were first thermally cleaned at 850°C, 100 A GaAs buffer layers were then grown at low substrate temperatures and, finally, 1.5 µm GaAs layers were grown at 600°C. It was found that the first thermal cleaning of Si is important in growing single domain GaAs and the growth temperatures of the buffer layer had to be low to get a good morphological surface.

Effects of the Substrate Offset Angle on the Growth of GaAs on Si Substrate

In the growth of GaAs on Si, the effects of the offset angle of the substrate and its direction on the epitaxial layer were studied using spherical Si substrates. The growth was carried out by a low pressure MOCVD system. On the grown layer, milky lines were observed along the [010] and the [001] axis of the substrate. Except for the narrow regions along these milky lines, the grown layer showed a mirror-like surface with a single domain structure. The surface morphology and the etch pit density in the single domain GaAs layer were strongly affected by the offset direction as well as the offset angle of the substrate.

Fabrication of GaAs MESFET Ring Oscillator on MOCVD Grown GaAs/Si(100) Substrate

GaAs MESFET ring oscillators were successfully fabricated on silicon substrate. GaAs epitaxial layers were grown directly by MOCVD on Si(100) substrate. A typical transconductance of 200 mS/mm was observed for the FET of 1.0 µm × 10 µm gate. A minimum propagation delay time of 51 ps/gate at a power dissipation of 1.1 mW/gate was observed for an E/D gate ring oscillator with gate length of 1.0 µm.

Growth of vanadium-doped semi-insulating GaAs by MOCVD

Semi-insulating GaAs layers have been grown by MOCVD by vanadium (V) doping with triethoxylvanadyl: VO(OC2H5)3. The resulting resistivity was 108 Ω cm or more at room temperature. The maximum deep level concentration found was more than 1018 cm-3 without surface roughening. Semi-insulating layers were obtained over a wide range of growth conditions and were obtained over a wide range of growth conditions and were relatively stable to high temperature treatment. Furthermore, this dopant did not show a memory effect.

The Dependence of Threshold Voltage Scattering of GaAs MESFET on Annealing Method

The threshold voltage scattering of GaAs metal-semiconductor field-effect transistors (MESFETs) fabricated on commercially available LEC-grown undoped semi-insulating GaAs substrate was investigated with varied annealing methods. It was found that the threshold voltage scattering greatly depended on annealing method. SiO2 capped annealing under arsenic vapor pressure allowed very uniform threshold voltage of GaAs MESFETs over the full water.

Improved Transconductance of AlGaAs/GaAs Heterostructure FET with Si-Doped Channel

The n+ self-alignment process with a furnace annealing was applied to the fabrication of heterostructure FETs. Maximum transconductance of 350 mS/mm and the K-value of 430 mA/V2 mm were obtained for the HMT structure (Lg=0.7 µm) at room temperature. An intentionally doped channel structure was also studied. An extremely high transconductance of 440 mS/mm and an extremely high K-value of 520 mA/V2 mm were obtained for this structure, suggesting that the performances of HEMTs mainly depend on the capacitance between the gate electrode and the confinedelectron gas.

Influence of Annealing Method on Microscopic One-to-One Correlation between Threshold Voltage of GaAs MESFET and Dislocation

We have investigated the influence of the annealing method on the correlation between dislocations and the threshold voltage (Vth) of metal-semiconductor field-effect transistors fabricated on liquid encapsulated Czochralski grown undoped semi-insulating GaAs substrate. For the annealing under low arsenic pressure, a one-to-one correlation betweenthe Vth and the dislocations is found and the Vth becomes lower within about a 70 µm radius around the clustered dislocations. For the annealing with arsenic overpressure by AsH3 or with plasma chemical vapor deposited SiNx cap, the Vth is not affected by the dislocations. These results indicate that the Vth is affected by the distribution of stoichiometry of substrates.