Kazuaki Ohshima

RFCPUs on glass and plastic substrates fabricated by TFT transfer technology

On the basis of the fabrication of a CPU on glass as a digital circuit presented in B. Lee et al. (2003) and T. Ikeda et al. (2004), as well as the fabrication of a flexible CPU using a TFT transfer technology presented in T. Takayama et al. (2004), we have succeeded in the development of the worlds first flexible RFCPUs (8bit, passive type) by adding to the CPU an antenna, an analog circuit, an encryption function and an RFID function, which operate using an RF signal with a frequency of 13.56MHz

A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor

A flip-flop achieving high-speed backup utilizing a Si transistor and long-term retention with zero standby power by means of a transistor of c-axis aligned crystalline (CAAC) In-Ga-Zn oxide, a kind of CAAC oxide semiconductor, featuring extremely low off-state current is proposed. Using the flip-flop, a 32-bit processor has been fabricated with 350-nm Si/180-nm CAAC oxide semiconductor technology, and demonstrated data backup and power shutdown in 1.5 clock cycles at a low power of 1.77 nJ, data recovery in 2.5 clock cycles, and data retention with zero standby power for at least a day. According to simulation results, fast backup and long-term retention can also be achieved with 45-nm Si/180-nm CAAC oxide semiconductor technology.

Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating

A chip of embedded SRAM having backup circuits using a 60-nm c-axis aligned crystalline oxide semiconductor (CAAC-OS) such as CAAC indium-gallium-zinc oxide (CAAC-IGZO) and Cortex-M0 core having flip-flops with CAAC-OS backup circuits is fabricated. The SRAM and M0 core can retain data using the backup circuits during power-off; thus, they can perform power gating (PG) with backup time of 100 ns and recovery time of 10 clock cycles (including data restoration time (100 ns)). Further, memory cell area and performance in combining a 45-nm Si SRAM memory cell with 60-nm CAAC-OS are estimated to have negligible overhead.

SRAM with c-axis aligned crystalline oxide semiconductor: Power leakage reduction technique for microprocessor caches

SRAM with backup circuits using a crystalline oxide semiconductor (OS) (e.g., a c-axis aligned crystalline oxide semiconductor (CAAC-OS) typified by CAAC In-Ga-Zn oxide (CAAC-IGZO)) is reported. Results of cell-level simulation based on 45-nm Si/100-nm OS process technology show backup time of 3.9 ns, recovery time of 2.0 ns, and break-even time of 21.7 ns. The OS-SRAM cell can replace a standard-SRAM cell without area overhead, which does not significantly affect normal operation. A 32-bit microprocessor test chip (350-nm Si/180-nm OS technology) with cache memory including the OS-SRAM was fabricated to demonstrate the intended normal and power-gating operations. The test chip demonstrated 97.6% standby power saving.

State retention flip flop architectures with different tradeoffs using crystalline indium gallium zinc oxide transistors implemented in a 32-bit normally-off microprocessor

As leakage power continues to increase when transistor sizes are downscaled, it becomes increasingly hard to achieve low power consumption in modern chips. Normally-off processors use state-retention and non-volatile circuits to make power gating more efficient with less static power. In this paper, we propose two novel state-retention flip-flop designs based on a parallel and series retention circuit architectures utilizing crystalline indium gallium zinc oxide transistors, which can achieve state retention with zero static power. To demonstrate the application of these different designs, they are implemented in a 32-bit normally-off microprocessor with an energy break-even time of 1.47 µs for the parallel type design and 0.93 µs for the series type design, at a clock frequency of 15 MHz. We show that decreasing the power supply duty cycle to 0.9%, the average current of the processor core can be decreased by over 99% using either type of flip-flop.

A normally-off microcontroller unit with an 85% power overhead reduction based on crystalline indium gallium zinc oxide field effect transistors

A low-power normally-off microcontroller unit (NMCU) having state-retention flip-flops (SRFFs) using a c-axis aligned crystalline oxide semiconductor (CAAC-OS) such as indium gallium zinc oxide (IGZO) transistors and employing a distributed backup and recovery method (distributed method) is fabricated. Compared to an NMCU employing a centralized backup and recovery method (centralized method), the NMCU employing the distributed method can be powered off approximately 75 µs earlier after main processing and can start the main processing approximately 75 µs earlier after power-on. The NMCU employing the distributed method can reduce power overhead by approximately 85% and power consumption by approximately 18% compared to the NMCU employing the centralized method. The NMCU employing the distributed method can retain data even when it is powered off, can back up data at high speed, and can start effective processing immediately after power-on. The NMCU could be applied to a low-power MCU.