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Dive into the research topics where Kazuharu Yamato is active.

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Featured researches published by Kazuharu Yamato.


IEEE Transactions on Reliability | 1982

Variance-Importance of System Components

Kyoichi Nakashima; Kazuharu Yamato

The paper defines the variance-importance of a component as the product of a relative sensitivity coefficient of component variance and the variance of component-unreliability estimate. Variance-importance is useful for identifying components that appreciably contribute to the uncertainty of system unreliability.


IEEE Transactions on Reliability | 1977

Optimal Design of a Series-Parallel System with Time-Dependent Reliability

Kyoichi Nakashima; Kazuharu Yamato

The paper formulates an optimal reliability design problem for a series system made of parallel redundant subsystems. The variables for optimization are the number of redundant units in each subsystem and the reliability of each unit. There is a cost-constraint. The time for which the system reliability exceeds a specified value is to be maximized. Similarly the cost could be minimized for a constraint on the mission time and reliability. A solution method for the formulated problems is presented along with an example.


IEEE Transactions on Computers | 1993

Some fundamental properties of multiple-valued Kleenean functions and determination of their logic formulas

Yutaka Hata; Kyoichi Nakashima; Kazuharu Yamato

Multiple-valued Kleenean functions that are models of a Kleene algebra and are logic functions expressed by logic formulas composed of variables, constants, and logic operations AND OR, and NOT are discussed. The set of Kleenean functions, is a model with the largest number of logic functions among existing models of a Kleene algebra, such as fuzzy logic functions, regular ternary logic functions, and B-ternary logic functions. Mainly, it is shown that any p-valued Kleenean function is derived from a monotonic ternary input functions and any p-valued unate function is derived from a unate binary input function. The mapping relations between them and the method to determine the logic formula of the Kleenean function and unate function from that of the monotonic ternary input function and unate binary input function, respectively, are classified. 7-or-less-valued Kleenean functions and unate functions of 3-or-fewer variables are enumerated. It is known that the number of p-valued Kleenean functions increases stepwise and that of unate functions increases smoothly as p becomes larger. >


international symposium on multiple-valued logic | 1993

Gate model networks for minimization of multiple-valued logic functions

Yutaka Hata; Takahiro Hozumi; Kazuharu Yamato

The use of gate model networks as a logic minimization method for multiple-valued logic functions is proposed. The gate model network is a kind of neural network constructed like and AND-OR two-level circuits using two gate models: an AND type gate model and an OR type gate model. The backpropagation (BP) method is used to train the network until it realizes the minimal solution. A solution is derived from the weights and thresholds. The gate model networks are applied to binary AND-OR circuit minimization and to the multiple-value max-of-mins expression minimization. It is shown that the gate model network is also applicable to minimize multiple-valued sum-of-products expressions, where sum refers to TSUM.<<ETX>>


international symposium on multiple-valued logic | 1989

A necessary and sufficient condition for multiple-valued logical functions representable by AND, OR, NOT, constants, variables and determination of their logical formulae

Yutaka Hata; T. Sato; Kyoichi Nakashima; Kazuharu Yamato

A necessary and sufficient condition is derived for p-valued logical functions representable by logical formulas built from variables, constants 0,1....p-1, and the logical operations AND, OR, and NOT (p-valued LR-functions). A method for determining a logical formula for p-valued LR-functions is presented. since the method deals only with 3/sup n/ input vectors, it gives the logical formulas easily.<<ETX>>


international symposium on multiple-valued logic | 1993

A repairable and diagnosable cellular array on multiple-valued logic

Naotake Kamiura; Yutaka Hata; Kazuharu Yamato

A diagnosable and repairable k-valued cellular array is proposed, assuming a single fault, i.e., either a stuck-at-0 fault or a stuck-at-(k-1) fault of switches, occurs in the array. By building in a duplicate column iteratively, a fault-tolerant array can be constructed for the stuck-at-(k-1) fault, therefore, since the stuck-at-(k-1) fault need not be diagnosed, the diagnosis is simple and easy. Furthermore, the array can be repaired easily by a systematic procedure. A comparison with other rectangular arrays shows that the present array has advantages with respect to the number of cells and steps for generating all test inputs.<<ETX>>


soft computing | 1996

3D automatic extraction method of the brain regions aided by fuzzy matching techniques

Syoji Kobashi; Naotake Kamiura; Yutaka Hata; Kazuharu Yamato

In the field of medical science, the extraction of the brain regions from MR images is valuable to diagnose an Alzheimers disease. We propose here a novel approach to extract the brain region using the fuzzy matching technique. We describe a modeling of the intensity histogram by fuzzy logic and evaluate fuzzy matching techniques for the extraction of the brain region. We develop the extraction algorithm based on a standard region growing technique. An experimental result on 36 MRI data shows that the error rate is 2.4%, on the average, against manually extracted volumes by a medical doctor.


international symposium on multiple-valued logic | 1992

Easily testable multiple-valued cellular arrays

Naotake Kamiura; Yutaka Hata; Fujio Miyawaki; Kazuharu Yamato

An easily testable k-valued cellular array consisting of input arrays and a control array that requires fewer cells than other methods is proposed. Stuck-at, open, and AND bridging faults are treated under the assumption that a single fault occurs in the array. Test input vectors can be easily generated from control inputs that specify the switches of cells. It is shown that a faulty cell can be effectively diagnosed by using several observable terminals and (k+1)-valued logic values.<<ETX>>


international symposium on multiple-valued logic | 1997

Multiple-valued programmable logic arrays with universal literals

T. Utsumi; Naotake Kamiura; Yutaka Hata; Kazuharu Yamato

A universal literal is a single-variable function and has an ability to manipulate more information than a set literal. The array size therefore could be eliminated by using universal literal generators (ULGs for short) in programmable logic arrays (PLAs), compared to PLAs with set literals. This paper discusses what operator is the most suitable in the term of eliminating the array size. We find four solutions as the good operator structures to eliminate the array size. A speculation of the upper bound of the array sizes is shown. Experiments are also done for randomly generated functions and some arithmetic functions. The experimental results show that the MAX-of-TPRODUCT form PLAs require the smallest array size.


international symposium on multiple valued logic | 1998

On concurrent tests of fuzzy controllers

Naotake Kamiura; Yutaka Hata; Kazuharu Yamato

In this paper, we propose concurrent tests of fuzzy controllers. We assume multiple stuck-at faults in membership functions. For tests of antecedent membership functions, we observe the sum of degrees by matching a current measured input with each function and that of degrees at several easily calculated co-ordinates. For tests of consequent ones, we observe the sum of their maximum degrees, that of degrees of applicability and that of degrees at several co-ordinates on the union of output fuzzy sets. We can find all the multiple faults except redundant ones. Our tests are superior to other tests in the number of additional membership functions and multiple fault detection.

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Kyoichi Nakashima

Toyama Prefectural University

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