Takahiro Hozumi

Gate model networks for minimization of multiple-valued logic functions

The use of gate model networks as a logic minimization method for multiple-valued logic functions is proposed. The gate model network is a kind of neural network constructed like and AND-OR two-level circuits using two gate models: an AND type gate model and an OR type gate model. The backpropagation (BP) method is used to train the network until it realizes the minimal solution. A solution is derived from the weights and thresholds. The gate model networks are applied to binary AND-OR circuit minimization and to the multiple-value max-of-mins expression minimization. It is shown that the gate model network is also applicable to minimize multiple-valued sum-of-products expressions, where sum refers to TSUM.<<ETX>>

An evolutionary computing approach to multilevel logic synthesis using various logic operations

This paper discusses the logic synthesis of multilevel circuits using various operations. We suppose target circuits having no loop back connections and usable any logic function in any part of the multilevel circuits. In this paper, we use MIN, MAX, TSUM and MODSUM functions as functions of logic gates. We minimize the circuit using the Genetic Algorithms. We encode each logic gate to the series of numbers representing a function and its connections and represent the circuit by a chromosome arranging the numbers for all logic gates. We show that our GAs can design a given function with more flexible structures.

On low cost realization of multiple-valued logic functions

This paper evaluates the number of product terms needed in the minimal sum-of-products expressions for extended product and sum operators based on Shannon expansion. We show definitions of a product-type and a sum-type function. According to the definitions, we list all product-type and sum-type functions by investigating all three-valued two-variable functions. Using the functions, we examine the numbers of product terms needed in the minimal sum-of-product expressions for any three-valued two-variable functions and show that the MODSUM-of-MINs expressions require fewest product terms of the all. On investigating all four-valued sum-of-products expressions, it is shown that MODSUM-of-MINs expressions require the fewest product terms. Furthermore, on investigating the expressions with the weak conditions for the product-type function. We find some expressions requiring fewer product terms than the MODSUM-of-MINs expressions.

The output permutation for the multiple-valued logic minimization with universal literals

This paper shows the effectiveness of an output permutation for the implementation of current-mode CMOS circuits. A combination of a simple function and an output permutation can realize a difficult function and cost for the combination will be lower than the cost for a difficult function. The output permutation can be realized by a universal literal and we can calculate the cost. We first examine the all combinations of universal literals and output permutations and show that some combinations can realize one-variable functions with lower costs. Next, we minimize two-variable functions and compare the costs with the costs obtained by some output permutations. As a result, we show that about 70% functions can reduce the costs and their reduction ratio is about 12% on average.

Design of Fuzzy Plas Using Fuzzy Decision Diagrams

ABSTRACTFuzzy PLAs can realize fuzzy logic functions that are composed of fuzzy AND, OR, NOT, and variables. In this article, first, four meaningful special classes of the fuzzy logic functions are introduced, and two types of fuzzy PLAs are demonstrated, one is an AND-OR fuzzy PLA and the other is an AND-OR/OR-AND fuzzy PLA. Next, we introduce a Fuzzy Decision Diagram and a Fuzzy Decision Diagram with Binary Terminals to design their fuzzy PLAs. We compare the column number on realizing their functions and clarify that an AND-OR/OR-AND fuzzy PLA has an advantage of hardware cost in the viewpoint of the requiring plane area.