Kazuhiko Iwasaki

Design of signature circuits based on weight distributions of error-correcting codes

Design techniques that can improve the aliasing probabilities of signature circuits for VLSI BIST (built-in self-test) are presented. The proposed techniques are based on the binary weight distributions of error-correcting codes over GF(2) and GF(2/sup m/). The technique considered for calculating the aliasing probability of signature circuits is appropriate for a vector supercomputer. Some of the calculations were done using the S810 supercomputer. The vectorization ratio of the program was 99.885% for an MISR (multiple-input signature register) with 16 inputs and for test length n=100-105.<<ETX>>

Aliasing probabilities and weight distributions of several codes

Signature testing is proposed for integrated circuit testing. One of the problems in signature testing is that not all the errors contained in the test response from the tested circuit can be detected (aliasing error). In this paper, the following results are shown: (1) utilizing the property of the maximum distance separable code, the aliasing probability of the multiple-input signature register (MISR) is formulated. It is shown that the aliasing error probability of the MISR does not depend on the selected polynomial. In addition, it is shown that there is no fluctuation as is observed in the case of single-input linear feedback shift registers (LFSR); (2) the aliasing error of the multiplexed MISR based on the primitive polynomials is analyzed using the weight distribution of the Reed-Solomon codes. It is also shown that there is no fluctuation as is observed in single-input LFRS; (3) the aliasing probability for single-input LFSR is analyzed using a computer program. It is verified that the aliasing probability of single-input LFSRs has different properties depending on the selected primitive polynomial. The fluctuation in the aliasing probability is observed.

Outline of Gmicro/200 and Memory Management Mechanism

This paper outlines the 32-bit microprocessor Gmicro/200 and its memory management mechanism on chip. This microprocessor’s target performance is 6 MIPS. To achieve this performance, a 6-stage pipeline, 5-unit distributed processing, 1-kbyte instruction cache, 128-byte stack cache, and 16-byte branch prediction table are used. The virtual memory management mechanism defined by the memory management unit (MMU) is 2-level paging with dual regions. the translation look-aside buffer (TLB) has 32 entries. It translates logical address within one machine cycle (50 ns) to physical address. The pipeline of the address translation and the external bus access cancels address translation delay.

Analysis of error-detecting probability of signature circuit for lsi self-testing and proprosal of new signature circuit

The self-testing method using a multiple-input signature register (MISR) has been proposed as a means of testing logic LSI. This paper analyzes the error-detecting ability when the MISR is used as a pattern compression circuit. Coding theory technique is applied in the analysis. As the first step, assuming that a Hamming code generating polynomial (primitive polynomial) is used as the polynomial in MISR, the error-detection rates are determined theoretically for single through quadruple errors. Then the error-detecting rates for single through quadruple errors are calculated for the modified Hamming code generating polynomial. It is indicated as a result that the multiple error-detection rate, especially the rate for the double error, does not reach 100%. In order to improve the multiple error-detection rate, a reversely dual MISR is proposed in which a pair of MISRs is used with opposite shift directions. When the Hamming code generating polynomial is employed as the polynomial in the reversely dual MISR, it is shown that single and double errors are always detected. The rate of triple error detection is calculated. It is also shown that if the modified Hamming code generating polynominal is used, all single, double and triple errors are detected.

A uniform network for VLSI massively parallel computers

Symmetrical Network Topologies (SNTs) for VLSI massively parallel computers are proposed. VLSI massively parallel computers can be expected to integrate more than dozens of processing elements. It is desired that the network in such a VLSI system is regular. SNT consists of a two-dimensional end-around mesh with supplementary symmetrical branch connections, and therefore, it satisfies the condition of regularity. In this paper it is shown that the SNTs have desirable characteristics with regard to diameter and average distance. That is, the SNTs have smaller diameters and average distance compared to the hypercubes with the same number of nodes. For example, for 4096 nodes, the degree, diameter and average distance of a hypercube are 12, 12 and 6.001, respectively. The degree, diameter and average distance of the SNT can be 8, 8 and 5.324, respectively. It is shown also that SNTs are maximally connected graphs resulting in a fault-tolerant network. Results show that SNTs are well suited for the VSLI implementation of massively parallel computers.

Decoding method for shortened fire codes and its application to VLSI processor

The disc system is one of the areas of applications for the error-correcting code. For this purpose, a Fire code with the generating polynomial G(x) = (xc + 1) × p(x) is frequently used. This paper considers the shortened Fire code, where the length of the code can be reduced according to the length of the record used. A decoding method suitable for VLSI is proposed. It is noted that the content of the feedback shift register with p(x) as the divider returns to the original pattern when it is shifted by the period e of p(x), and the speed is improved by ignoring the integer multiple shifts of e. This decoding method requires less hardware (i. e., shift registers and counters), and has the merits of easiness in design and expandability, according to the record length. The principle is expanded to the general cyclic code. The proposed decoding method is implemented on the hard disc controller (peripheral LSI for HDC 16 bit microcomputers). A 32-bit Fire code is used. For a typical record length of 512 bits in the disc system, the speed was comparable to that of the high-speed decoding. The error-correcting part is composed of 6700 Tr, which is 5.2% of the whole system (129 kTr). This figure demonstrates the practical usefulness of the proposed method in VLSI design.