Tsuneo Funabashi

Decoding method for shortened fire codes and its application to VLSI processor

The disc system is one of the areas of applications for the error-correcting code. For this purpose, a Fire code with the generating polynomial G(x) = (xc + 1) × p(x) is frequently used. This paper considers the shortened Fire code, where the length of the code can be reduced according to the length of the record used. A decoding method suitable for VLSI is proposed. It is noted that the content of the feedback shift register with p(x) as the divider returns to the original pattern when it is shifted by the period e of p(x), and the speed is improved by ignoring the integer multiple shifts of e. This decoding method requires less hardware (i. e., shift registers and counters), and has the merits of easiness in design and expandability, according to the record length. The principle is expanded to the general cyclic code. The proposed decoding method is implemented on the hard disc controller (peripheral LSI for HDC 16 bit microcomputers). A 32-bit Fire code is used. For a typical record length of 512 bits in the disc system, the speed was comparable to that of the high-speed decoding. The error-correcting part is composed of 6700 Tr, which is 5.2% of the whole system (129 kTr). This figure demonstrates the practical usefulness of the proposed method in VLSI design.