Kazuhiko Mishima

Alignment sensor corrections for tool-induced shift (TIS)

As the most critical semiconductor device geometries shrink down to the quarter micron order, requirements for overlay accuracy also become increasingly critical in the actual semiconductor manufacturing process. Factors in overlay error (especially, alignment error) originate in the interaction of process and tool. It is therefore necessary to improve alignment accuracy from both the process and the tool sides. In an effort to solve this as a tool supplier, we at Canon must minimize tool factors to reduce alignment errors caused by the interaction of process and tool factors. We though that we needed some evaluation criteria with such interaction take into account, and redefined the concepts of tool induced shift and wafer induced shift as a criterion. This paper introduces these new concepts and discusses validity of the criteria showing experimental results of alignment accuracy implementing the idea in the real process.

New projection optics and aberration control system for the 45-nm node

The 65nm and the subsequent 45nm node lithography require very stringent CD control. To realize high-accuracy CD control on an exposure tool, it is essential to reduce wavefront aberrations induced by projection optics design and manufacturing errors and then stabilize the aberrations while the exposure tool is in operation. We have developed two types of new hyper-NA ArF projection optics to integrate into our new platform exposure tool: a dry system and a catadioptric system for immersion application. In this paper, aberration measurement results of these projection systems are shown, demonstrating that ultra-low aberration is realized. In addition, a new projection optical system has been developed which incorporates high degree-of-freedom Aberration Controllers and automatic aberration measuring sensors. These controllers and sensors are linked together through Aberration Solver, a software program to determine optimal target values for aberration correction, thereby allowing the projection optics to maintain its best optical properties. The system offers excellent performance in correcting aberrations that come from lens heating, and makes it possible to guarantee extremely low aberrations during operation of the exposure tool.

The solutions for 3D-NAND processes with Canon's latest KrF scanner

The NAND type flash-memory is now used not only on smart phones or tablet PCs, but also adopted on infrastructures such as servers, etc.

Nanoimprint system development for high-volume semiconductor manufacturing the and status of overlay performance

Imprint lithography has been shown to be a promising technique for replication of nano-scale features. Jet and Flash Imprint Lithography* (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Included on the list are overlay, throughput and defectivity. The most demanding devices now require overlay of better than 4nm, 3 sigma. Throughput for an imprint tool is generally targeted at 80 wafers per hour. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. The purpose of this paper is to report the status of throughput and defectivity work and to describe the progress made in addressing overlay for advanced devices. In order to address high order corrections, a high order distortion correction (HODC) system is introduced. The combination of applying magnification actuation to the mask, and temperature correction to the wafer is described in detail and examples are presented for the correction of K7, K11 and K17 distortions as well as distortions on actual device wafers.