Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Seiya Miura is active.

Publication


Featured researches published by Seiya Miura.


Proceedings of SPIE | 2007

New projection optics and aberration control system for the 45-nm node

Toshiyuki Yoshihara; Bunsuke Takeshita; Atsushi Shigenobu; Yasuo Hasegawa; Yoshinori Ohsaki; Kazuhiko Mishima; Seiya Miura

The 65nm and the subsequent 45nm node lithography require very stringent CD control. To realize high-accuracy CD control on an exposure tool, it is essential to reduce wavefront aberrations induced by projection optics design and manufacturing errors and then stabilize the aberrations while the exposure tool is in operation. We have developed two types of new hyper-NA ArF projection optics to integrate into our new platform exposure tool: a dry system and a catadioptric system for immersion application. In this paper, aberration measurement results of these projection systems are shown, demonstrating that ultra-low aberration is realized. In addition, a new projection optical system has been developed which incorporates high degree-of-freedom Aberration Controllers and automatic aberration measuring sensors. These controllers and sensors are linked together through Aberration Solver, a software program to determine optimal target values for aberration correction, thereby allowing the projection optics to maintain its best optical properties. The system offers excellent performance in correcting aberrations that come from lens heating, and makes it possible to guarantee extremely low aberrations during operation of the exposure tool.


Proceedings of SPIE | 2012

A study of vertical lithography for high-density 3D structures

Shinichiro Hirai; Nobuyuki Saito; Yoshio Goto; Hiromi Suda; Kenichiro Mori; Seiya Miura

In recent years, demand for high-density integration of semiconductor chips has steadily increased due to miniaturization and high-performance requirements of electronics including Smartphones and Tablet PCs. In addition to 3D integration using Through-Silicon Via (TSV) technology, 2.5D integration technology using silicon interposers has also become a hot topic. Canon has identified key challenges that must be solved for successful implementation of high-density integration technologies into mass production and to meet these challenges, Canon developed the FPA-5510iV i-line lithography tool (stepper) that is now in wide use at customer sites for their most challenging processes. In this paper, Canon will explain details of FPA-5510iV features that support high-density integration. Canon will also introduce additional challenges that must be solved to ensure the success of high-density integration technologies in mass production, as well as Canon efforts to solve the remaining challenges.


china semiconductor technology international conference | 2016

Photolithography study for high-density integration technologies

Hiromi Suda; Masaki Mizutanf; Shinichiro Hirai; Kenichiro Mori; Seiya Miura

In recent years, demand for high-density integration of semiconductor chips has steadily increased due to miniaturization and high-performance requirements of electronics including Smartphones and Tablet PCs. In addition to 3D integration using Through-Silicon Via (TSV) technology and 2.5D integration technology using silicon interposers, Fan-Out Wafer Level Packaging (FOWLP) using redistribution processes over chip size has become a hot topic these days. Canon has identified key challenges that must be solved for successful implementation of high-density integration technologies into mass production and to meet these challenges, Canon developed the FPA-5510iV i-line lithography tool which is now widely used at customer sites. In this paper, we will explain details of FPA-5510iV features that support high-density integration, additional challenges that must be solved for successful implementation of high-density integration technologies in mass production and Canons efforts to solve the remaining challenges.


international conference on electronics packaging | 2016

Photolithography study for advanced packaging technologies

Hiromi Suda; Masaki Mizutani; Shinichiro Hirai; Kenichiro Mori; Seiya Miura

In recent years, demand for high density integration of semiconductor chips has steadily increased due to miniaturization and high-performance requirements of electronics including Smartphones and Tablet PCs. In addition to 3D integration using Through Silicon Via (TSV) technology and 2.5D integration technology using silicon interposers, Fan-Out Wafer Level Packaging (FOWLP) using redistribution processes over chip size has become a hot topic these days. Canon has identified key challenges that must be solved for success of high density integration technologies into mass production and to meet these challenges, Canon developed the FPA-5510iV i-line lithography tool which is now widely used at customer sites. In this paper, we will explain details of FPA-5510iV features that support high density integration, additional challenges that must be solved for successful implementation of high-density integration technologies in mass production and Canons efforts to solve the remaining challenges.


china semiconductor technology international conference | 2015

The solution to enhance i-line stepper applications by improviing process overlay accuracy

Atsushi Shigenobu Yuhei Sumiyoshi; Ryo Sasaki; Yasuo Hasegawa; Kentaro Ushiku; Hirotaka Sano; Bunsuke Takeshita; Seiya Miura

Canon has developed the worlds first stepper with the shot shape compensator called “SSC”, which independently controls x and y magnification of shots on a wafer. This SSC function enables steppers to achieve overlay accuracy equivalent to scanners. The most suitable application of this function is back side illumination (BSI) image sensors, which has large distortion on wafers because of bonding and thinning processes. In this paper, we will provide the detailed descriptions along with the exposure results using our new solutions.


Proceedings of SPIE | 2014

The solution to enhance i-line stepper applications by improving mix and match process overlay accuracy

Yuhei Sumiyoshi; Ryo Sasaki; Yasuo Hasegawa; Kentaro Ushiku; Hirotaka Sano; Atsushi Shigenobu; Bunsuke Takeshita; Seiya Miura

In recent years, the demand for high sensitivity image sensors has become prominent, in correlation with the reduction of pixel size and higher pixel counts. Sensitivity is especially important for mobile applications and as a result, back side illumination (BSI) structure image sensors are emerging. The spread of BSI image sensors causes new technological challenges in the lithographic process. One of the challenges is related to the wafer distortion created during the bonding and thinning of the wafer. The challenge is to reduce the impact of the wafer distortion on the overlay accuracy, and we propose two unique solutions for this challenge: Extended Advanced Global Alignment (EAGA) and Shot Shape Compensator (SSC). EAGA is an alignment measurement function that can measure the position and shape of all shots on the wafer. SSC is an exposure function that adjusts the shape of exposure shots according to the shape of the underlying layers shot on the distorted wafer, by controlling both the XY magnification difference and skew component of the projection optical system. In order to realize the SSC system in i-line stepper, Canon has introduced a new compensation mechanism featuring “two-dimensional Alvarez” optical elements. One other challenge is to detect alignment marks located on the back surface of the silicon wafer and for this challenge, Canon has employed a new alignment system using infrared light. In this paper, we will provide detailed descriptions along with exposure results using these solutions. We will also delve into the possibility of additional process applications that can benefit from the enhanced overlay accuracy provided by Canon i-line lithography systems.


Archive | 1994

Surface inspecting device

Seiya Miura; Michio Kohno


Archive | 1997

Method and apparatus for inspecting a surface state

Seiya Miura; Michio Kohno; Nobuhiro Kodachi


Archive | 1996

Surface inspecting device using bisected multi-mode laser beam and system having the same

Seiya Miura; Michio Kohno; Takehiko Iwanaga


Archive | 1995

Inspection system for original with pellicle

Minoru Yoshii; Michio Kohno; Seiya Miura; Kyoichi Miyazaki; Toshihiko Tsuji; Seiji Takeuchi

Collaboration


Dive into the Seiya Miura's collaboration.

Researchain Logo
Decentralizing Knowledge