Kazuhiko Taketa
Sanyo
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Featured researches published by Kazuhiko Taketa.
international solid-state circuits conference | 2003
Hideki Yamauchi; Shigeyuki Okada; Kazuhiko Taketa; T. Ohyama; Yuh Matsuda; Tsugio Mori; T. Watanabe; Yoshihiro Matsuo; Y. Yamada; T. Ichikawa; Yoshifumi Matsushita
A one-chip image processor for next-generation digital cameras and broadband PDA multimedia mobile phones is described. It is capable of processing JPEG2000 data with 30 frames/s and a 27 MHz operating frequency. The process is fabricated in 0.25 /spl mu/m CMOS and contains 8.5M transistors in a 103 mm/sup 2/ area.
international solid state circuits conference | 2005
Hideki Yamauchi; Shigeyuki Okada; Kazuhiko Taketa; Yuh Matsuda; Tsugio Mori; T. Watanabe; Yoshihiro Matsuo; Yoshifumi Matsushita
This paper describes techniques and approaches capable of achieving real-time motion-JPEG2000 encoding/decoding of high definition images with low power consumption. We propose a highly efficient VLSI implementation of procedure of two-dimensional wavelet transform that uses intermediate results through wavelet calculation. Double data-BUS and double encoder architecture with cross data flow is also introduced in order to make an improvement in coding performance and power consumption. The processor performs compression of 1440 /spl times/ 1080 pixels images with the speed of 30 frames per second (fps) at a required operating frequency as low as 54 MHz. A test chip of this implementation has been fabricated in a 0.18-/spl mu/m 5-layer CMOS process. The chip is 9.2 /spl times/ 9.2 mm/sup 2/ in size and consumes 0.9 W when supplied with 1.8 V and 54 MHz.
international solid-state circuits conference | 2004
Hideki Yamauchi; K. Mochizuki; Kazuhiko Taketa; T. Watanabe; Tsugio Mori; Yuh Matsuda; Yoshifumi Matsushita; A. Kobayashi; Shigeyuki Okada
The Motion-JPEG 2000 codec processor uses 0.18/spl mu/m technology. It integrates 18.6M transistors on a 92mm/spl times/9.2mm die and performs both decoding and compressing of 1440/spl times/1080 pixels with 30frames/s at 54MHz. A tile size obtained is 4096/spl times/2048 pixels and is sufficient for transmitting an HD movie. The IC runs up to 104MHz and dissipates 400mW at 1.8V and 54MHz.
IEEE Translation Journal on Magnetics in Japan | 1985
Isao Yasuda; Yorinobu Yoshisato; Hideki Yoshikawa; Kazuhiko Taketa; T. Yazaki
The crosstalk, electromagnetic conversion, and service life characteristics of two-channel gap inline heads with Sendust bulk head structures (track width 60 ¿m, gap 0.2 ¿m) are discussed. When the mutual inductance between heads M is small, crosstalk occurs during reproduction but not during recording. By reducing the core size, M was reduced, lowering the crosstalk level during reproduction. Studies of the gap depth dependence of the reproduction output indicated that reducing the gap depth by 20 ¿m would only result in an output increase of 3 dB, but would have adverse effects on the head life and reliability due to friction.
Archive | 2011
Kazuhiko Taketa; Shigeyuki Okada
Archive | 2007
Shigeyuki Okada; Kazuhiko Taketa
international solid-state circuits conference | 2002
Hideki Yamauchi; Shigeyuki Okada; Kazuhiko Taketa; Yuh Matsuda; Tsugio Mori; T. Watanabe; Yasoo Harada; Morio Matsudaira; Yoshifumi Matsushita
international conference on consumer electronics | 2001
Hideki Yamauchi; Shigeyuki Okada; Kazuhiko Taketa; Yoshikazu Mihara; Yasoo Harada
Archive | 1985
Yorinobu Yoshisato; Hideki Yoshikawa; Kazuhiko Taketa; Isao Yasuda; Kenji Kubota; Kazuhiko Takahashi
Archive | 1985
Isao Yasuda; Yorinobu Yoshisato; Hideki Yoshikawa; Kazuhiko Taketa