Shigeyuki Okada

32.2: A Real-Time 2-D to 3-D Image Conversion Technique Using Computed Image Depth

The “Computed Image Depth method” (CID) is proposed for converting from all kinds of twodimensional (2D) images into three dimensional (3D) images. The 3D images are generated by computing the depth of each separated area of the 2D images with their contrast, sharpness and chrominance. The CID is implemented into a single-chip LSI with the “Modified Time Difference method” ‘*l. In this implementation, both methods are used adaptively according to the object’s motions in the images. The 2D-to-3D image conversion system with this newly developed LSI realizes to generate 3D images automatically in real-time.

Image processor capable of block-noise-free JPEG2000 compression with 30 frames/s for digital camera applications

A one-chip image processor for next-generation digital cameras and broadband PDA multimedia mobile phones is described. It is capable of processing JPEG2000 data with 30 frames/s and a 27 MHz operating frequency. The process is fabricated in 0.25 /spl mu/m CMOS and contains 8.5M transistors in a 103 mm/sup 2/ area.

1440 /spl times/ 1080 pixel, 30 frames per second motion-JPEG 2000 codec for HD-movie transmission

This paper describes techniques and approaches capable of achieving real-time motion-JPEG2000 encoding/decoding of high definition images with low power consumption. We propose a highly efficient VLSI implementation of procedure of two-dimensional wavelet transform that uses intermediate results through wavelet calculation. Double data-BUS and double encoder architecture with cross data flow is also introduced in order to make an improvement in coding performance and power consumption. The processor performs compression of 1440 /spl times/ 1080 pixels images with the speed of 30 frames per second (fps) at a required operating frequency as low as 54 MHz. A test chip of this implementation has been fabricated in a 0.18-/spl mu/m 5-layer CMOS process. The chip is 9.2 /spl times/ 9.2 mm/sup 2/ in size and consumes 0.9 W when supplied with 1.8 V and 54 MHz.

An 81 MHz, 1280 /spl times/ 720pixels /spl times/ 30frames/s MPEG-4 video/audio CODEC processor

A high-definition MPEG-4 CODEC processor capable of encoding 720p images (1280/spl times/720 pixels 30f/s) at 81MHz is presented. The CODEC is implemented with only 390k gates and an 80 kB SRAM. It is fabricated in a 0.13/spl mu/m CMOS process on a 5.6mm/spl times/5.6mm die.

A Single Chip Motion JPEG Codec LSI

We have developed a single chip motion JPEG codec LSI that can compress and decompress VGA-size (640 pixels/spl times/480 lines) JPEG images at the rate of 30 frames per second simply by connecting a single external buffer memory chip. The LSI can control compression ratio control technique to store a fixed number of images when there is limited memory capacity, and it compresses data stored in the frame buffer to enable high-speed signal processing without the use of high-speed image memory. The JPEG codec core is small (40000 gates) and power consumption is low (220 mW), making it well suited to a wide range of image processing applications in consumer products.

A 1440/spl times/1080 pixels 30frames/s motion-JPEG2000 codec for HD movie transmission

The Motion-JPEG 2000 codec processor uses 0.18/spl mu/m technology. It integrates 18.6M transistors on a 92mm/spl times/9.2mm die and performs both decoding and compressing of 1440/spl times/1080 pixels with 30frames/s at 54MHz. A tile size obtained is 4096/spl times/2048 pixels and is sufficient for transmitting an HD movie. The IC runs up to 104MHz and dissipates 400mW at 1.8V and 54MHz.

A single chip MPEG1 decoder

A single chip MPEG1 decoder was developed. It contains a video decoder, an audio decoder and a system decoder for MPEG1 and also include a CD-ROM decoder for a package media application. The outstanding feature of the chip is its high quality control of MPEG1 system such as buffer management and AV synchronization. The chip basically decodes a MPEG1 stream automatically with minimal support from an external microprocessor. The circuits were designed using a dedicated hardwired logic resulting in a low cost and low power chip. The chip was fabricated in triple metal 0.5 micron CMOS technology. It dissipates about 400 mW power with 54 MHz clock and 3.3 V voltage supply. >

System-on-a-chip for digital still cameras with VGA-size video clip shooting

An advanced, compact, and energy efficient system-on-a-chip has been developed that permits a single chip to perform all of the necessary functions for a DSC (digital still camera). Quality VGA-size motion pictures can be recorded at a rate of 30 fps (frames per second).

Ultra Small HD Video Camera Using MPEG4 Codec with SD Memory Card as Storage

We developed an ultra small HD video camera that can capture 720P/30 fps video movie and a 5.1 M pixel still image simultaneously. A new HD MPEG4 codec enables to record 23 minutes of HD video on a 2 GB SD memory card. A full-color organic EL is applied as a display with many better features than LCDs.

One-chip 15 frame/s mega-pixel real-time image processor

A-one-chip 15 frame/s mega-pixel real time image processor, for mobile multimedia applications is presented. It contains mega-pixel CCD signal processing, a motion-JPEG/MPEG2 image compression/decompression engine, a RISC-CPU, an NTSC encoder, a SDRAM controller and peripheral interfaces.