Kazuhiro Adachi

High channel mobility in normally-off 4H-SiC buried channel MOSFETs

We have fabricated buried channel (BC) MOSFETs with a thermally grown gate oxide in 4H-SiC. The gate oxide was prepared by dry oxidation with wet reoxidation. The BC region was formed by nitrogen ion implantation at room temperature followed by annealing at 1500/spl deg/C. The optimum doping depth of the BC region has been investigated. For a nitrogen concentration of 1/spl times/10/sup 17/ cm/sup -3/, the optimum depth was found to be 0.2 /spl mu/m. Under this condition, a channel mobility of 140 cm/sup 2//Vs was achieved with a threshold voltage of 0.3 V. This channel mobility is the highest reported so far for a normally-off 4H-SiC MOSFET with a thermally grown gate oxide.

8.5 m/spl Omega/ /spl middot/ cm/sub 2/ 600-V double-epitaxial MOSFETs in 4H-SiC

The most important issue in realizing a 4H-SiC vertical MOSFET is to improve the poor channel mobility at the MOS interface, which is related to high on-resistance. This letter focuses on a novel 4H-SiC vertical MOSFET device structure where a low acceptor concentration epitaxial layer is used as a channel. We call this structure a double-epitaxial MOSFET (DEMOSFET). In the structure, the p-well is composed of two p-type epitaxial layers, while an n-type region between the p-wells is formed by low-dose n-type ion implantation. A buried channel is formed at the surface of the upper p/sup

Improvement of unipolar power device performance using a polarization junction

/epitaxial layer. A fabricated DEMOSFET showed an on-resistance of 8.5 m/spl Omega//spl middot/cm/sup 2/ at a gate voltage of 15 V and a blocking voltage of 600 V. This on-resistance is the lowest so far reported for a vertical MOSFET with a blocking voltage of 600 V.

Single Material Ohmic Contacts Simultaneously Formed on the Source/P-Well/Gate of 4H-SiC Vertical MOSFETs

A concept, polarization junction (PJ), for overcoming the trade-off relationship between the area-specific on-resistance and the breakdown voltage of unipolar power devices is presented. The PJ concept is based on the charge compensation of positive and negative polarization charges at heterointerfaces. The PJ has a similar effect as superjunction without impurity doping. The performance of GaN-based conventional devices and PJ devices have been compared using numerical device simulations. Area-specific on-resistance of PJ devices became less than 1∕10 than that of conventional devices for the breakdown voltage higher than 300V.A concept, polarization junction (PJ), for overcoming the trade-off relationship between the area-specific on-resistance and the breakdown voltage of unipolar power devices is presented. The PJ concept is based on the charge compensation of positive and negative polarization charges at heterointerfaces. The PJ has a similar effect as superjunction without impurity doping. The performance of GaN-based conventional devices and PJ devices have been compared using numerical device simulations. Area-specific on-resistance of PJ devices became less than 1∕10 than that of conventional devices for the breakdown voltage higher than 300V.

Design consideration for high output power density (OPD) converter based on power-loss limit analysis method

We fabricated 4H-SiC vertical MOSFETs with contacts to the source, p-well and polycrystalline silicon (polysilicon) gate and these were simult aneously formed from a single material, using one deposition and a single contact annealing process. T ypical specific contact resistances of 4.8×10 -5 cm for the n source region, 1.5×10 -6 cm for the gate polysilicon and 5.2×10 cm for the p-well contact region were obtained using Al/Ni (Al~6%) a s the contact metal. Also, the static characteristics of the vertic al MOSFETs indicated that the MOS interface can withstand an even higher temperature process such as that u ed in ohmic-contact formation. 1.Introduction A widely used technique to form low resistivity ohmic contacts on SiC is to deposit materials such as an Ni [1] for the n-type region and a Ti/Al [2] for the p-t ype region, followed by postdeposition annealing (PDA). It has commonly been thought that it is difficult to form ohmic contacts from a single material on both nand p-type SiC, since a metal having a low-barrier height on an n-type SiC has a high-barrier height on a p-type SiC, and the reverse is also true. However, in the production of SiC power MOSFETs, we urgently need to uti lize he technology to form ohmic contacts on both the n + source and p-well, using a single contact material because it can directly contribute to miniaturizing cell size, resulting in lower specific on-resistance (R on,sp). Nevertheless, a single material contact for practical devices ha s not been discussed to date. This paper describes a simple fabrication process and c ont ct properties that are especially suited to form the ohmic contacts on the n + source, p-well and gate polysilicon in 4H-SiC vertical MOSFETs, using a single contact material. In addition, we discuss the formation of a back side contact that is used as a drain electrode. 2.Device Design and Processing Figure 1 (a) shows a schematic cross section and (b) a plan view of the vertical MOSFET we designed and fabricated. The n + source and p-well contact p + region were formed adjacent to each other in an identical contact window. Also, thin Ni [1] or layered Al/Ni [3] as a c ont t material was formed on the bottom of the contact window to the n + source and p-well contact p region and n + gate polysilicon. An alloyed Ni as a drain electrode was formed on the ground and polished back side of the substrate. The MOS channel length, define d by the p* on leave from Nissan Research Center (NRC), Yokosuka, Japan ** also with NRC Materials Science Forum Online: 2003-09-15 ISSN: 1662-9752, Vols. 433-436, pp 669-672 doi:10.4028/www.scientific.net/MSF.433-436.669

The Theoretical Study on Total Power Dissipation of SiC Devices in Comparison with Si Devices

Design consideration for a future high output power density converter has been carried out with a power device loss model. The power device loss model has been established by the power-loss limit analysis method which estimates total power loss of semiconductor power devices accurately taking the correlation between circuit stray parameters and device power losses into consideration. An advantage of the design is highly-detailed volume and an output power density of a converter can be estimated quantitatively by using the power device loss model. Optimal configuration of a power converter constructed by conversion circuit part, passive components and a DC-link capacitor was investigated on the thermal problem by the method. Availability of the method was confirmed by the quantitative design of a 3 kVA DC-AC converter constructed by a Si-MOSFET and a SiC-Shottky barrier diode (SBD) hybrid pair

Hot Electron Induced Current Collapse in AlGaN/GaN HEMTs

The trade-off between breakdown voltage, Vbr and a specific on-state resistance, Rons of SiC devices is several hundred times better than the equivalent Si devices, due to SiC having a higher critical electric field, Ec. However, this evaluation method is only valid for the static on-state loss characteristics of devices. It is important to determine the advantage of SiC devices considering the total power dissipation in the device including switching loss for the practical use of the devices. The product of Rons and a stored charge Qo in a drift region, RonQo corresponding to switching loss has been recognized as a general figure of merit for power device evaluations [1-3]. In this paper a total power dissipation, Pt, defined as a summation of a on-state loss, Pon, a gate driving loss, Pi and a switching loss, Po, is theoretically studied, considering the figure of merit. The purpose of this paper is to reinforce the advantages of 4H-SiC uni-polar devices in comparison with equivalent Si devices and outline the technical issues to be solved for these advantages to be realized. Theory and Calculation The total charges stored in the drift region inside a device structure at the maximum drain voltage, Vdmax is given by, c o E Q ε = max [C/cm 2 ]. (Eq.1) This shows that Qomax is determined by material properties. When the switching device turns off, the drain voltage, Vd rises to the bus voltage, i.e. a maximum drain charge Vdmax and the specific capacitive energy stored is given by,

SiC Device Limitation Breakthrough with Novel Floating Junction Structure on 4H-SiC

The mechanism of drain current collapse in AlGaN/GaN high electron mobility transistors (HEMTs) was investigated. Current collapse was clearly observed for TiO2 passivated HEMTs. However, no evidence of current collapse was apparent for SiNx passivated HEMTs. This suggests that AlGaN surface traps play a major role in current collapse. The experimental results were compared with numerical device simulation results. The device simulations were performed taking into account hot electron generation and deep traps at the AlGaN surface. The simulated drain current transients were consistent with the degradation and recovery behavior of the experimental results. These results indicate that current collapse is caused by the trapping of hot electrons in deep levels at the AlGaN surface.

Fabrication of 4H-SiC Double-Epitaxial MOSFETs

A novel floating Junction Structure with a Schottky Barrier Diode based on 4H-SiC has been simulated using Technology Computer Aided Design (TCAD). T his paper discusses the advantages of this structure in comparison with conventi al and super-junction structures, the R ons and Vbr characteristics with varying structural parameters, and ov erc ming the SiC material limitation. The results show that R ons is reduced by 66% and it is proved that the breakthrough occurs at voltages between 4 and10KV, at which the R ons places in the gap between the bipolar and unipolar devices, by the utilization of a floating junct io . The floating junction structure is simpler to fabricate than the super-junction structur e and is a practical method to overcome the material limitations of 4H-SiC. Introduction 4H-SiC SBD with n-type epitaxial layer are suitable for voltages up to 4KV. Since the majority of the on-resistance (R ons) is the resistance of the epi layer, its reduction becomes the cri ical design issue for power electronic devices. An effective way of reduc ing the bulk resistance may be an application of the super-junction (SJ) structure, which is based on the c harge compensation concept [1-3]. However in reality the SJ has difficulties, i.e., 1) the char ge must strictly be controlled in the pillars, otherwise the breakdown voltage (V br) decreases rapidly, 2) deep doping into bulk to make pillars is required to minimize the number of iteration processes, and 3) as the total imbalanced charge increases with pillar depth, the realization of high voltage devices becomes increasingly difficult. Since, for 4H-SiC the control of activation rate of dopant into lattice is very diffi cult, the SJ is not suitable due to the ease in which charge imbalance occurs . Also it is very difficult to make deep implantation due to crystalline damage caused by the high energy implants. It is hoped to overcome these issues in the novel structure, the f loating junction (FJ), which seeks to lower the bulk resistance [4-7]. The FJ is based on a concept th at the triangular electric field distribution in the bulk is divided into several sections to decrease the magnitude of the peak field, by inserting electrically floating p + buried layers in n-type bulk (Fig.1). As the charge in the p + layer must remain at the breakdown voltage, FJ only requires the satisfac tion of Qa>Qd, unlike Qa=Qd as required in the SJ devices. Accordingly the FJ does not suffer from the difficulties of the SJ. 1) no need for strict control of charge, 2) no need of deep doping due to separatio n of buried layer, and 3) no limitation of realizing high voltage device due to unrelation wi th charge balance. Hence the structure FJ has great advantages over SJ. The results prove that the excellent performance of the FJ st ructure with one floating junction shows a 66% reduction of R ons with optimized floating junction pattern. This indicates the Materials Science Forum Online: 2003-09-15 ISSN: 1662-9752, Vols. 433-436, pp 887-890 doi:10.4028/www.scientific.net/MSF.433-436.887

Fabrication of Double Implanted (0001) 4H-SiC MOSFETs by using Pyrogenic Re-Oxidation Annealing

The most important problem in a 4H-SiC vertical MOSFET is the high on-resistance caused by low channel mobility. This study focuses on a novel device structure named double-epitaxial MOSFET (DEMOSFET). In this device, the p-well is composed of two p-type epitaxial layers, while n-type region, between the p-wells, is formed by low dose n-type ion implantation. Buried channel is formed in the low concentration upper p-type layer. The high acceptor concentration of the bottom p-type layer and the low dose implanted n-type region supports the high breakdown voltage. The fabricated DEMOSFET exhibits an on-resistance of 36 mΩcm at gate voltage of 20 V and a blocking voltage of 1150 V. The on-resistance has positive temperature dependence at gate voltage higher than 15V.