Kazuhisa Yamada

PROTEUS: programmable hardware for telecommunication systems

This paper discusses a new architecture for programmable hardware targeted at high-speed digital telecommunication systems and describes a preliminary design. The basic architecture of the programmable hardware is proposed based on the characteristics of functions and an analysis of logic used in actual communication subsystems performing high-speed bit level operations. The proposed architecture, called PROTEUS, includes a pipeline structure of logic and latch groups, and a 2-stage logic block structure that consists of small LUTs and wide gates. The design strategy of a prototype chip and the CAD techniques used to achieve the required performance are also discussed.<<ETX>>

Special purpose FPGA for high-speed digital telecommunication systems

A new FPGA (Field Programmable Gate Array) is developed for high-speed digital telecommunication systems. As architecture is based on the fundamental characteristics extracted from an analysis of actual systems. The FPGA has several unique features for realizing high-speed transport data processing. It allows us to build the high-performance components that are frequently used in transport data processing. In addition, its inter-chip connection mechanism enables us to build flexible multi-FPGA modules. Furthermore, we introduce a dedicated CAD system for the FPGA. We design several actual transport processing circuits on the FPGA using the CAD system and evaluate them. Experimental results show that the device has the potential to realize practical systems.

Reconfigurable real-time signal transport system using custom FPGAs

The paper discusses a new architecture for reconfigurable real time signal transport systems that uses FPGAs and describes an experimental system design. The basic architecture of the reconfigurable transport system is proposed based on the requirements for real time signal transport in a typical telecommunication network. The proposed system consists of reconfigurable modules using the custom designed FPGA called PROTEUS, a program control module for hardware/software coprocessing, and line interface modules including an automatic connection control mechanism. The system can be used not only for the initial installation stages of actual communication systems, but also for rapid prototyping tools or emulators.

Performance improvement technique for synchronous circuits realized as LUT-based FPGAs

This paper presents a new technique for improving the performance of a synchronous circuit configured as a look-up table based FPGA without changing the initial circuit configuration; only the register location is altered. It improves clock speed and data throughput at the expense of latency. One of the most significant benefits realized by this approach is that the time-consuming and user-uncontrollable reconfiguration processes, i.e., remapping, replacement, and rerouting, are unnecessary when improving circuit performance. After applying our technique to some benchmark circuits, the average performance improvement was 33% for six combinational circuits, and 25% for 18 sequential circuits. >

A novel approach to real-time verification of transport system design using FPGA based emulator

This paper discusses a new approach to efficient system design verification that uses an FPGA based real-time emulator. The architecture of a real-time emulator suitable for high-speed digital transmission system emulation and an experimental system are described. The proposed system consists of an emulation engine using the custom designed multi-chip module FPGA called PROTEUS-MCM, a program control unit, and a physical interface. The system can be used not only for real-time emulation of high-speed transmission systems, but also as initial systems for actual communication networks.

FORM: a frame-oriented representation method for digital telecommunication system design

This paper proposes a new design method called FORM (Frame-Oriented Representation Method) for digital telecommunication systems with the aim of efficient system design and development. FORM has the unique feature wherein timing design and function design are performed independently. FORM can translate system-level specifications at the behavioral level into RTL. This method is applied to the SDH/ATM interface and it is proved that FORM relaxes design complications and simplifies system design.

New application of FPGAs to programmable digital communication circuits

This paper proposes a new design method to construct flexible, high performance digital communication systems. The method, called Amphibious Logic, combines top-down design with high level synthesis and reconfigurable hardware. The methods capability and problems that had to be solved associated are discussed. Design examples using the high level CAD system called PARTHENON and conventional FPGAs are illustrated. The results show that it is possible to create programmable, high performance digital communication circuits with the proposed method.

A novel approach to realizing flexible transport systems using reconfigurable hardware

This paper discusses a novel approach to realizing a flexible high speed signal transport system for the multimedia network. We propose a flexible transport system architecture based on reconfigurable hardware. The proposed architecture realizes all the functions needed for high speed telecommunication systems which include physical interfaces, programmable buffer memory, bi-directional processing, multiclock processing and co-processing using dedicated processors for higher layer processing. We develop an experimental prototype system using the custom designed reconfigurable hardware called PROTEUS. We also discuss a design methodology for achieving flexible transport systems. Experimental results for 156 Mbps SDH/ATM processing circuits are shown. Our experimental results show the feasibility of achieving both flexibility and high speed processing in high speed digital transport systems.

Telecommunication-Oriented FPGA and Dedicated CAD System

We developed a telecommunication-oriented LUT-based FPGA and its dedicated CAD system. The FPGA, called PROTEUS, has some unique features. For example, its logic block structure enables the user to easily realize the basic components used in telecommunication circuits such as binary counters and pattern matching circuits. In addition, PROTEUS has a lot of regularly-placed latches to accomplish pipelined data processing. With a logic synthesis system, the CAD system offers a top-down design methodology. The programming data downloaded into PROTEUS can be obtained directly from RTL language descriptions. Furthermore, the CAD system supports hardware-macro-based design to realize high performance circuits. In this paper, we introduce the PROTEUS FPGA architecture and CAD system. In addition, we show some experimental results proving that PROTEUS is applicable to real telecommunication circuits.

A Speed-Up Technique for Synchronous Circuits Realized as LUT-Based FPGAs

This paper presents a new technique for improving the performance of a synchronous circuit configured as a look-up table based FPGA without changing the initial circuit configuration except for latch location. One of the most significant benefits realized by this approach is that the time-consuming and user-uncontrollable reconfiguration processes, i.e., re-mapping, re-placement and re-routing, are unnecessary to improve circuit performance.