Kazuki Tateoka

A high efficiency GaAs MCM power amplifier for 1.9 GHz digital cordless telephones

A GaAs MCM power amplifier has been developed for 1.9-GHz digital cordless telephones. Power-added efficiency of 40.2% and P/sub 1dB/ of 22.2 dBm have been obtained at drain supply voltage of 3.6 V. Adoption of the MCM structure and on-chip ferroelectric capacitors has successfully reduced the GaAs total chip area to be 1.1 mm/sup 2/.<<ETX>>

A GaAs single balanced mixer MMIC with built-in active balun for personal communication systems

A GaAs single balanced mixer IC with built-in active baluns for IF and LO inputs has been developed. The present mixer achieved the conversion gain of 16 dB and the LO signal suppression over 30 dBc at the LO input power of 0 dBm. Owing to a novel BST (Barium Strontium Titanate) capacitor technology, the implemented mixer IC was packaged in the small 6 pin outline with the extremely small chip size of 0.6/spl times/0.65 mm/sup 2/. The IC can eliminate the LO filter of the up-conversion system for a variety of handyphone-sets in L-band.<<ETX>>

A GaAs MCM power amplifier of 3.6 V operation with high efficiency of 49% for 0.9 GHz digital cellular phone systems

Extremely small GaAs PA has been implemented using the AlN multilayer MCM for 0.9 GHz digital cellular phones. The present PA exhibited the efficiency of 49% with drain supply voltage as low as 3.6 V. The PA was designed to provide the matching circuits with the maximum gain at the input and the minimum intermodulation distortion at the output.<<ETX>>

A miniaturized GaAs power amplifier for 1.5 GHz digital cellular phones

An extremely miniaturized GaAs PA has been developed for the application in 1.5-GHz Japanese digital cellular phones. By using MuMIC (i.e. multilayer microwave integrated circuit) technology, the half sized (0.2 cc) PA with 1.1 W output power has successfully been implemented. The 48-% power-added efficiency has been obtained with drain supply voltage of 3.5-V.

A novel GaAs power MESFET with low distortion characteristics employing semi-insulating setback layer under the gate

A low distortion GaAs power MESFET has been developed by employing a semi-insulating setback layer under the gate. The setback region was obtained by diffusing chromium from the Cr/Pt/Au gate metal in self-aligned manner. The novel power FET with the setback layer was found to be insensitive to surface trapping effects. They showed only 5-6 percent frequency dispersion of drain current at 1 MHz compared to DC condition. Because of this small frequency dispersion, the typical measurement FET, which has a surface setback layer, with a gate width of 36 mm exhibited 1.5 dB larger output power at 1 dB gain compression point than that of the FET without the setback layer. Moreover, in the /spl pi//4 shift-QPSK modulation that has been most popular in digital mobile communication system, the FET exhibited 11 dB smaller adjacent channel leakage power than the conventional one at the output power of 31.5 dBm.