Kazumasa Morishita

Mask data processing technique using GPU for reducing computer cost

The computer cost for mask data processing grows increasingly more expensive every year. However the Graphics Processing Unit (GPU) has evolved dramatically. The GPU which originally was used exclusively for digital image processing has been used in many fields of numerical analysis. We developed mask data processing techniques using GPUs together with distributed processing that allows reduced computer costs as opposed to a distributed processing system using just CPUs. Generally, for best application performance, it is important to reduce conditional branch instructions, to minimize data transfer between the CPU host and the GPU device, and to optimize memory access patterns in the GPU. Hence, in our optical proximity correction (OPC), the light intensity calculation step, that is the most time consuming part of this OPC, is optimized for GPU implementation and the other inefficient steps for GPU are processed by CPUs . Moreover, by fracturing input data and balancing a computational road for each CPU, we have put the powerful distributed computing into practice. Furthermore we have investigated not only the improvement of software performance but also how to best balance computer cost and speed, and we have derived a combination of the CPU hosts and the GPU devices to maximize the processing performance that takes computer cost into account . We have also developed a recovery function that continues OPC processing even if a GPU breaks down during mask data processing for a production. By using the GPUs and distributed processing, we have developed a mask data processing system which reduces computer cost and has high reliability.

Study of ELS technology for random logic LSI toward 32-nm node

There has been an ongoing request to make semiconductor devices smaller and smaller. The cellblock size of SRAM is predominated by both a gate-to-contact space and a poly-to-poly space. The gate-to-contact space is defined by the leakage value from the poly electrode. So we focused on the poly-to-poly space for all shrinkage. We have been studying connected line splitting techniques. We named it ELS (end of line splitting) technology. A critical issue is to control gaps between two narrow gate-polys line-ends or between a narrow gatepolys line-end and a neighboring wire-poly line due to lower contrast in low-k1 lithography. In the case of standard cells, especially, the patterning of narrow gate-poly projected to wire-poly is easy to shorten. To prevent this electrical short, designers avoid keeping a narrow gap and small chip size. In order to realize a narrower gap, a splitting technique, well-known and adopted in polys line-ends of SRAM that are regularly arrayed, is effective. We are investigating how to extend this technique as ELS technology for random logic of poly toward creating a 32-nm node. In this paper, the authors focus on the following topics: 1) data preparation technique, and 2) experimental results. Then this technology for the poly layer of random logic LSI devices is compared with result of conventional single exposure and double pattering technology. In addition, the result that overlay control issue for ELS technology is not severe compared with pitch doubling technology is described. ELS technology can help the designer and our lithographer to reduce the gap and reduce the array grid size of standard cells.