Tatsuo Chijimatsu

New double exposure technique without alternating phase-shift mask

The double exposure technique using alternating phase shift mask (alt-PSM) has been proposed and it is well used for the gate layer of the high performance logic devices as strong resolution enhancement technology (RET). This technique has advantage that the fine resist profile is obtained on wafer with extensive process margin. However, this double exposure technique is very expensive because of the alt-PSM cost. This time, the new double exposure technique without alt-PSM is developed for gate layer of 45 nm node logic devices. In this new double exposure method, attenuated phase shift mask (att-PSM) or binary mask (BIM) is used with dipole illumination. It is thought that this new double exposure method is effective for random logic devices which have various pattern pitches by the optimization of dipole illumination condition and pattern placement. Firstly, the optical contrast and depth of focus (DOF) is calculated. From these results, dipole illumination condition is optimized. It is found that DOF of new double exposure method is wider than that of conventional method. In addition, mask pattern is optimized to obtain wide process margin. For dense pattern, mask biasing is effective and optimization of shifter width is effective for isolated pattern. Furthermore, it is found that assist pattern is very effective for isolated pattern. From experimental results, it is proved that new double exposure method have wider process margin than that of conventional one. The strong design for manufacturing (DFM) rule that required the severe line width control is placed at single direction is proposed to realize the new double exposure method. Finally, it is found that the lithographic performance of new double exposure method has same level as conventional method with alt-PSM for gate layer of 45 nm logic devices.

Stress stabilization of β‐tantalum and its crystal structure

We studied the relationship between Ta crystal structures and the stress stability of Ta under heating. The stress in Ta which was sputter deposited on SiC was unstable and changed more than 2×109 dyn/cm2 to the compressive side during heating at 200 °C for 30 min in air. In contrast, the stress in Ta which was sputter deposited on SiC whose surface was modified by Ar sputtering was very stable, and the stress change was less than 1.5×108 dyn/cm2 even after 6 h of heating at 200 °C. The x‐ray diffraction patterns of the Ta revealed that stable Ta was strongly (002) oriented β‐Ta, and that unstable Ta was randomly oriented β‐Ta with some α‐Ta. We found that amorphizing the SiC surface or inserting a thin amorphous interlayer enhanced growth of strongly (002) oriented β‐Ta.

Practical method of evaluating two-dimensional resist features for lithographic DRC

The optical proximity effect becomes significant near the practical resolution limit of photolithography, depending on the wavelength and numerical aperture of the stepper. Recently, VLSI design rules have almost reached their limits. Larger ICs cannot be designed and be manufactured without using a lithographic DRC (design rule check) tool or an OPC (optical proximity correction) tool. Therefore, it has become necessary to develop a technology which can accurately predict resist features from the designed circuit layout. We studied deviation in both the line width and the length due to proximity effect and investigated the phenomena. Also we developed a technology which can accurately predict the behavior of the proximity effect from an aerial image. This technology is based on a simple threshold model. We optimized the calculations for an aerial image and the threshold of intensity in order to predict deviations in the line width and length. We also considered the profile of an aerial image to predict the critical point. The calculations for an aerial image and threshold which we optimized in this manner can be used to predict 2D patterns.

Implementation of attenuated PSMs in DRAM production

We studied the use of attenuated phase shift mask (PSM) in DRAM production. There exists several problems with the use of an attenuated PSM compared to a conventional Cr mask. These include a need to form an opaque region, facilitate reticle alignment with a stepper, and optimize mask bias to prevent side peak printing. First, we investigated the characteristics of checkerboard patterns in achieving an opaque region. We confirmed the feasibility of making a mask to maintain opaqueness. Next we developed a mask fabrication process so to enable reticle alignment in some kinds of steppers by using an additional Cr layer under the attenuated layer. Finally, we tried to implement attenuated PSM in a previous generation stepper. We found that we must pay attention to lens aberration when optimizing mask bias.

Mask data processing technique using GPU for reducing computer cost

The computer cost for mask data processing grows increasingly more expensive every year. However the Graphics Processing Unit (GPU) has evolved dramatically. The GPU which originally was used exclusively for digital image processing has been used in many fields of numerical analysis. We developed mask data processing techniques using GPUs together with distributed processing that allows reduced computer costs as opposed to a distributed processing system using just CPUs. Generally, for best application performance, it is important to reduce conditional branch instructions, to minimize data transfer between the CPU host and the GPU device, and to optimize memory access patterns in the GPU. Hence, in our optical proximity correction (OPC), the light intensity calculation step, that is the most time consuming part of this OPC, is optimized for GPU implementation and the other inefficient steps for GPU are processed by CPUs . Moreover, by fracturing input data and balancing a computational road for each CPU, we have put the powerful distributed computing into practice. Furthermore we have investigated not only the improvement of software performance but also how to best balance computer cost and speed, and we have derived a combination of the CPU hosts and the GPU devices to maximize the processing performance that takes computer cost into account . We have also developed a recovery function that continues OPC processing even if a GPU breaks down during mask data processing for a production. By using the GPUs and distributed processing, we have developed a mask data processing system which reduces computer cost and has high reliability.

Study for lithography techniques of hybrid mask shape of contact hole with 1.35NA polarized illumination for 28nm-node and below logic LSI

In this presentation, the advantage in the use of combination of polarized illumination and technique of optimum shape mask for contact-hole lithography will be discussed. Both simulation and experimental work were carried out to characterize performance of this technique. We confirmed that some polarized illuminations show improvement in image contrast, MEEF, and DOF for nested contact-hole than non-polarized condition. In addition, certain shape mask shows more improvement. Totally 63% DOF improvement from traditional square shape with nonpolarized condition was confirmed. In final single exposure era for contact-hole, this result with techniques of hybrid mask shape and polarized illumination is very attractive.

Poly-width-modification method for canceling layout-dependent characteristic variations for low-standby-power CMOS technologies

Due to increase of integration density on a chip, layout variations have a serious impact on MOSFET behavior, such as active-area-size dependence (the STI-stress effect), well-boundary location dependence (the well-proximity effect) and other proximity effects. A circuit MOSFET model (An extracted SPICE-parameter set) tends to have complex expressions. Circuit designers, however, require a sufficiently tuned SPICE-parameter set even at the early stage of technology development. In particular, accuracy of MOSFET-off-current estimation is essential to low-standby-power products like cellular phones. We propose a practical method of MOSFET-characteristic correction for the difference between the final silicon characteristics and the early extracted SPICE-parameter set. This is a simple and reasonable method which is to perform the final modification of gate-poly width taking into account layout-proximity dependence. This method enables real concurrent development by solving a problem of the inconsistency of silicon and SPICE parameters.

Improvement of Simulation Accuracy Using a Non Gaussian Kernel

We compared a simulators predictions with the critical dimension (CD) value measured on the wafer. We used sub resolution assist features (SRAF) in the experiment to keep the focus margin, the minimum size of the mask was small and comparable with the absorbers thickness. Therefore, it seems that we need a rigorous model and a variety of parameters for high prediction accuracy. We investigated the prediction error and found its behavior was not complicated. The dependence of the prediction errors was related to the space until the next feature, but the relationship was not linear; rather, it went up and down periodically like a Bessel function. This fact gave us the idea that it might be possible to improve the simulation accuracy by using a special convolution kernel but not a Gaussian function. We used a complementary kernel and tried to find a suitable shape to match the prediction error. The convolution kernel consisted of a complex number in order to represent phase change and amplitude loss. The kernel was applied to the simulators mask plain. The results showed a significant improvement in simulation accuracy and a reduction in the route mean square (RMS) of the CD fitting error for all features with or without SRAFs. We used this model for optical proximity correction (OPC) and verified its accuracy with a printed wafer image. The range of the final CD variation of 40 nm line on the wafer was 1.9 nm, and the model also showed good agreement with the experimental two-dimensional feature shape.

Study of ELS technology for random logic LSI toward 32-nm node

There has been an ongoing request to make semiconductor devices smaller and smaller. The cellblock size of SRAM is predominated by both a gate-to-contact space and a poly-to-poly space. The gate-to-contact space is defined by the leakage value from the poly electrode. So we focused on the poly-to-poly space for all shrinkage. We have been studying connected line splitting techniques. We named it ELS (end of line splitting) technology. A critical issue is to control gaps between two narrow gate-polys line-ends or between a narrow gatepolys line-end and a neighboring wire-poly line due to lower contrast in low-k1 lithography. In the case of standard cells, especially, the patterning of narrow gate-poly projected to wire-poly is easy to shorten. To prevent this electrical short, designers avoid keeping a narrow gap and small chip size. In order to realize a narrower gap, a splitting technique, well-known and adopted in polys line-ends of SRAM that are regularly arrayed, is effective. We are investigating how to extend this technique as ELS technology for random logic of poly toward creating a 32-nm node. In this paper, the authors focus on the following topics: 1) data preparation technique, and 2) experimental results. Then this technology for the poly layer of random logic LSI devices is compared with result of conventional single exposure and double pattering technology. In addition, the result that overlay control issue for ELS technology is not severe compared with pitch doubling technology is described. ELS technology can help the designer and our lithographer to reduce the gap and reduce the array grid size of standard cells.

Optimization of contact hole lithography for 65-nm node Logic LSI

Patterning of contact/via is a difficult issue for the optical lithography for each successive generation of LSIs. We examined a number of approaches to obtain a large process window and found that a dry ArF exposure tool with a large depth of focus (DOF) can form 100 nm contact holes. Our experimental results show that enough DOF can be obtained for various layouts by using sub-resolution assist feature (SRAF) technology and a unique illumination technology.