Kazunori Nemoto

Cycle-time improvements for photolithography process in semiconductor manufacturing

Cycle-time reduction is of great importance to semiconductor manufacturers. Photolithography, being one of the most repeated processes, is an area where substantial improvements can be made. We investigate the effects of various process control mechanisms for photolithography on the cycle-time at the process and at the overall fab via a simulation study. Test run policy at the photolithography station, test run frequency, duration of inspection, and machine dedication policy for the equipment are the factors we consider. Equipment down time due to preventive or breakdown maintenance and rework rates are also taken into account. Parallel testing, where test wafer is inspected while the lot is being processed, is the best policy in terms of cycle-time performance. Long inspection time and infrequent, long down times have the most adverse effects, but flexible machine assignment may reduce the impact of down times. Test run frequency is only significant for serial testing, where processing of the lot is not finished until the failed test wafer is stripped and reworked.

Process integration of single-wafer technology in a 300-mm fab, realizing drastic cycle time reduction with high yield and excellent reliability

In this paper, we discuss a new technology implemented with single-wafer processing for a 300-mm fab. Newly developed equipment and chemicals reduce the process time and provide cost savings. The combination of fully automated systems and single-wafer processing significantly reduces queuing time. The process has been re-integrated to eliminate long time processes and make it suitable for single-wafer technologies. As a result, a very aggressive cycle time (0.25 days/layer) with high yield, in double-polysilicon, sextuple-metal, 0.18-/spl mu/m logic process has been demonstrated. High-performance devices with excellent reliability are also obtained. A new methodology for detecting parametric errors effectively in the early stages of production is implemented for quick yield ramp up.

Impact of Silicon Surface Roughness on Device Performance and Novel Roughness Measurement Method

Since higher performance of semiconductor devices is required, all of the semiconductor wafer manufacturers make their effort into device size reduction. However, in the latest semiconductor device, only the size reduction is not sufficient to achieve the requirement. The carrier mobility is essential to be improved. The semiconductor manufacturers, especially wet cleaning process people, try to optimize their process parameters to get smoother silicon surface. When they examine the process parameters, only Atomic Force Microscope (AFM) is available to measure the roughness of silicon surface, but the throughput of AFM is quite low. To solve this problem, we present a method of measuring silicon surface roughness called micro-haze measurement. Through experiments and a correlation analysis, we confirmed that it is sensitive enough to monitor silicon surface roughness in a much shorter time than the conventional method.

Repair yield simulation with iterative critical area analysis for different types of failure

We propose a general method for repair yield estimation based on critical area analysis using a commercial Monte-Carlo simulator. We classify failures into several types according to the repair rules and use iterative critical area analysis for each type of failure (ICAA-ETF) to calculate the repair yield. Our proposed method makes it possible to accurately estimate within a few hours the repair yield of a memory product. An example of application to an actual SRAM product is discussed to illustrate in detail how our method can be used for critical area calculation and repair yield modeling.

A new systematic yield ramp methodology

This paper presents a systematic yield ramp methodology that is based on defect reduction. The proposed approach uses statistical regression analysis to find the origin of the defects associated with yield loss. Moreover, in order to verify its usefulness, the proposed methodology is applied to high volume memory device production resulting in yield improvement due to shortening the time required for defect elimination.

An effective method for yield enhancement using zonal defect recognition

This paper presents a zonal defect recognition algorithm that can be applied to the problem of automated defect recognition in semiconductor manufacturing, The algorithm uses digital image processing techniques and template matching to achieve a high recognition rate by classifying zonal defects into one of three defect types: clustered defects, gross defects, or repetitive defects. The feasibility of using the algorithm for automated detection was demonstrated experimentally. Application of the algorithm to actual production lines is expected to contribute to rapid yield ramp-up.

Quantifying the benefits of cycle time reduction in semiconductor wafer fabrication

In recent years, semiconductor manufacturing has become extremely complex due to device size reduction. Hence the manufacturing cycle time, also called turn around time (TAT), which is defined as the time required from wafer input through probing test, becomes longer year by year. This renders the delay between process defect occurrence and detection a significant problem. On the other hand, customer demands for faster delivery are increasing because their product life cycles are getting shorter. Therefore, TAT reduction is important for semiconductor manufacturers not only to satisfy customer requirements, but also to remain competitive in their market. This paper examines the financial benefits of TAT reduction using stochastic simulation.

Non-defective area analysis for quantifying yield impact

The present paper introduces a novel yield impact quantification method which is designed especially to have robustness to clustered defects and false detection by inspection tools. The yield impact can be obtained by non-defective area analysis of cumulative defect maps. The accuracy of the proposed method is discussed based on experimental results that were obtained using actual in-line inspection data. Application of the proposed method is contributing to rapid yield ramp-up.

Advanced Method for Monitoring Copper Interconnect Process

Stabilizing the copper interconnect process is the key to improving yield and reliability. A stable process for forming adequate grains in a copper film is important, but there is no proper method for monitoring the grains in that film. We introduce the micro-haze method, an advanced method for monitoring grain size using scattering light. We experimentally verified the effectiveness of the method and concluded that the method enables the monitoring the grains in a copper film.

Developing the new ADC algorithm that enables to identify the defect source

Since the semiconductor manufacturing process has become more and more complicated due to the introduction of either new materials or new structures, detecting the source of a defect has become dramatically difficult. Automatic Defect Classification (ADC) is one of the most effective ways for identifying the source of a defect. However, the current ADC algorithm is insufficient in identifying a defect source, because its classification results are quite simple. Since the classification is determined by the shape or size of the defect, it is difficult to figure out the process or processing tool in which the defects are generated. To solve this problem, we propose a new ADC algorithm and have already applied it to a high-volume System-on-Chip (SoC) production line to verify its efficiency. We confirmed with the classification results that the new ADC algorithm is almost as accurate as manually classifying them, but with the reduction of the time required for identifying the defect source.