Kazuo Imai

Characterization of phosphorus pile-up at the SiO2/Si interface

Phosphorus pile-up at the SiO 2 /Si interface and how its location affects n-well doping concentration are described. The pile-up is first shown to be situated on the SiO 2 side of the SiO 2 /Si interface, and then the amount of phosphorus involved is determined quantitatively. Doping concentration decreases during n-well processes, and the decrease is due to removal of the pile-up layer with removal of SiO 2

Detection of Phosphorus Pileup at SiO2 / Si Interface

Oxidizing phosphorus-doped silicon or annealing composite layers of silicon dioxide and phosphorus-doped silicon causes phosphorus pileup at the SiO 2 and Si interface. Neutron activation analysis of the phosphorous in an SiO 2 /Si sample fabricated by the oxidation of phosphorus-doped Si shows that most of the phosphorus which piles up is on the SiO 2 side of the interface

Copper Decoration Followed by TEM Observation Identifying Defects in the Buried Oxides of SOI Substrates

Copper decoration followed by transmission electron microscopy (TEM) observation is proposed for identifying defects in the buried oxides of silicon-on-insulator (SOI) substrates. This method comprises Si surface layer etching (i.e., exposure of the buried-oxide surface), oxide-defect location detection with copper decoration, and sample thinning for TEM observation and analysis. The advantage of copper decoration is that the electronic current needed for defect detection is very small, so the influence of the electronic current on the original oxide-defect structure can be minimized. Defects observed are categorized into four groups from the viewpoint of size and shape.

Study of a Veil Structure and a Two-Step Corrosion Suppression Process in Al–Si–Cu Etching

µ-Auger analysis of the veil structure produced during Al–Si–Cu etching indicates the presence of carbon, oxygen, aluminum, and chlorine in all regions of the structure and silicon in the outer region. A novel two-step etching method deyeloped based on the veil-structure analysis can suppress corrosion when using CF4, and O2+CF4 gas plasma. This method drastically decreases the corrosion density.

Thin-SOI Process Using Bonding and Etch-back Method without Epitaxial Growth

A new thin-SOI process is proposed. This process is classified as a single etch-stop method. It uses an etch-stopped layer as an active layer by decreasing boron concentration in the etch-stopped layer so that an epitaxial layer is not needed. The boron concentration in the 500-nm-thick p+ layer after etch-stopping is decreased from 7×1019 cm-3 to less than 2×1017 cm-3 by hydrogen annealing at 1100°C for 3 h. Additionally, surface roughness is decreased from 2.3 nm to about 0.2 nm. This value is almost equivalent to a polished wafer roughness. This process is simple and does not require complicated equipment, thus allowing for the manufacture of a low-cost SOIs.