Kazushige Kobayakawa | Researchain

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Featured researches published by Kazushige Kobayakawa.

Archive | 1993

Multiprocessor system including a transfer queue and an interrupt processing unit for controlling data transfer between a plurality of processors

Kazushige Kobayakawa; Shigeru Nagasawa; Masayuki Ikeda; Haruhiko Ueno; Naoki Shinjo; Teruo Utsumi; Masami Dewa; Kenichi Ishizaka

Archive | 1993

Transfer request queue control system using flags to indicate transfer request queue validity and whether to use round-robin system for dequeuing the corresponding queues

Kazushige Kobayakawa; Shigeru Nagasawa; Masayuki Ikeda; Haruhiko Ueno; Naoki Shinjo; Teruo Utsumi; Masami Dewa; Kenichi Ishizaka

Archive | 1996

Data communication system which guarantees at a transmission station the arrival of transmitted data to a receiving station and method thereof

Haruhiko Ueno; Shigeru Nagasawa; Masayuki Ikeda; Naoki Shinjo; Kenichi Ishizaka; Teruo Utsumi; Masami Dewa; Kazushige Kobayakawa

Archive | 1993

Method and apparatus for processing and transferring data to processor and/or respective virtual processor corresponding to destination logical processor number

Masayuki Ikeda; Shigeru Nagasawa; Naoki Shinjo; Teruo Utsumi; Masami Dewa; Haruhiko Ueno; Kazushige Kobayakawa; Kenichi Ishizaka

Archive | 1997

Multiprocessor system and parallel processing method for processing data transferred between processors

Masayuki Ikeda; Shigeru Nagasawa; Haruhiko Ueno; Naoki Shinjo; Teruo Utsumi; Kazushige Kobayakawa; Naoki Sueyasu; Kenichi Ishizaka; Masami Dewa; Moriyuki Takamura

Archive | 1995

Parallel processing system including instruction processor to execute instructions and transfer processor to transfer data for each user program

Masayuki Ikeda; Shigeru Nagasawa; Naoki Shinjo; Teruo Utsumi; Masami Dewa; Haruhiko Ueno; Kazushige Kobayakawa; Kenichi Ishizaka

Archive | 1997

Data transfer using local and global address translation and authorization

Masayuki Ikeda; Shigeru Nagasawa; Naoki Shinjo; Teruo Utsumi; Masami Dewa; Haruhiko Ueno; Kazushige Kobayakawa; Kenichi Ishizaka

Archive | 1993

Synchronous processing method and apparatus for a plurality of processors executing a plurality of programs in parallel

Masami Dewa; Shigeru Nagasawa; Masayuki Ikeda; Haruhiko Ueno; Naoki Shinjo; Teruo Utsumi; Kazushige Kobayakawa; Kenichi Ishizaka; Moriyuki Takamura

Archive | 1993

Transfer processor including a plurality of failure display units wherein a transfer process is prohibited if failure is indicated in a failure display unit

Naoki Shinjo; Shigeru Nagasawa; Masayuki Ikeda; Haruhiko Ueno; Teruo Utsumi; Kazushige Kobayakawa; Masami Dewa; Kenichi Ishizaka; Tadao Amada

Archive | 1995

Abnormal Packet Processing System

Teruo Utsumi; Shigeru C O Fujitsu L Nagasawa; Masayuki C O Fujitsu Lim Ikeda; Naoki Shinjo; Masami Dewa; Haruhiko C O Fujitsu Limi Ueno; Kazushige Kobayakawa; Kenichi Ishizaka

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