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Dive into the research topics where Teruo Utsumi is active.

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Featured researches published by Teruo Utsumi.


conference on high performance computing (supercomputing) | 1994

Architecture of the VPP500 parallel supercomputer

Teruo Utsumi; Masayuki Ikeda; Moriyuki Takamura

The VPP500 vector parallel processor is a highly parallel, distributed memory supercomputer that has a performance range of 6.4 to 355 gigaFLOPS and a main memory capacity from 1 to 222 gigabytes. The system scalably supports between 4 and 222 processors interconnected by a high-bandwidth crossbar network. Three key aspects of the VPP500, which are in sharp contrast to current massively parallel systems, characterize its architecture. First the building block is a 1.6 gigaFLOPS vector processor that is more than an order of magnitude faster than the processors used in massively parallel processors (MPP). This high uniprocessor performance reduces the dependence on parallelism. Second the distributed memory architecture and high-bandwidth crossbar network eliminate many of the bottlenecks found in MPP systems. These allow efficient utilization of hardware and have the effect of lessening the complexity of programming parallel computers. Third the system realizes high throughput by its capability to arbitrarily partition the processing elements for flexible multiprocessing.<<ETX>>


Archive | 1993

Multiprocessor system including a transfer queue and an interrupt processing unit for controlling data transfer between a plurality of processors

Kazushige Kobayakawa; Shigeru Nagasawa; Masayuki Ikeda; Haruhiko Ueno; Naoki Shinjo; Teruo Utsumi; Masami Dewa; Kenichi Ishizaka


Archive | 1993

Transfer request queue control system using flags to indicate transfer request queue validity and whether to use round-robin system for dequeuing the corresponding queues

Kazushige Kobayakawa; Shigeru Nagasawa; Masayuki Ikeda; Haruhiko Ueno; Naoki Shinjo; Teruo Utsumi; Masami Dewa; Kenichi Ishizaka


Archive | 1996

Data communication system which guarantees at a transmission station the arrival of transmitted data to a receiving station and method thereof

Haruhiko Ueno; Shigeru Nagasawa; Masayuki Ikeda; Naoki Shinjo; Kenichi Ishizaka; Teruo Utsumi; Masami Dewa; Kazushige Kobayakawa


Archive | 1993

Method and apparatus for processing and transferring data to processor and/or respective virtual processor corresponding to destination logical processor number

Masayuki Ikeda; Shigeru Nagasawa; Naoki Shinjo; Teruo Utsumi; Masami Dewa; Haruhiko Ueno; Kazushige Kobayakawa; Kenichi Ishizaka


Archive | 1997

Multiprocessor system and parallel processing method for processing data transferred between processors

Masayuki Ikeda; Shigeru Nagasawa; Haruhiko Ueno; Naoki Shinjo; Teruo Utsumi; Kazushige Kobayakawa; Naoki Sueyasu; Kenichi Ishizaka; Masami Dewa; Moriyuki Takamura


Archive | 1995

Parallel processing system including instruction processor to execute instructions and transfer processor to transfer data for each user program

Masayuki Ikeda; Shigeru Nagasawa; Naoki Shinjo; Teruo Utsumi; Masami Dewa; Haruhiko Ueno; Kazushige Kobayakawa; Kenichi Ishizaka


Archive | 1997

Data transfer using local and global address translation and authorization

Masayuki Ikeda; Shigeru Nagasawa; Naoki Shinjo; Teruo Utsumi; Masami Dewa; Haruhiko Ueno; Kazushige Kobayakawa; Kenichi Ishizaka


Archive | 1993

Synchronous processing method and apparatus for a plurality of processors executing a plurality of programs in parallel

Masami Dewa; Shigeru Nagasawa; Masayuki Ikeda; Haruhiko Ueno; Naoki Shinjo; Teruo Utsumi; Kazushige Kobayakawa; Kenichi Ishizaka; Moriyuki Takamura


Archive | 1993

Transfer processor including a plurality of failure display units wherein a transfer process is prohibited if failure is indicated in a failure display unit

Naoki Shinjo; Shigeru Nagasawa; Masayuki Ikeda; Haruhiko Ueno; Teruo Utsumi; Kazushige Kobayakawa; Masami Dewa; Kenichi Ishizaka; Tadao Amada

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