Kazutami Arimoto

Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System

A charge-recycling circuit and system that reuses the energy between two or more stacked CPUs is proposed in order to double the life of a battery. In this architecture, CPUs are divided into upper and lower load groups, and electrical charges are shared among the stacked CPUs and a tank capacitor. Charges are temporarily stored in the tank capacitor and are then reused. To control divided loads, a high-speed and energy-efficient regulator is needed. Internal circuit voltage variation between the upper and lower modules is determined by seven low-drop-out (LDO) regulators, a voltage-boosting capacitor circuit, and the tank capacitor. As a result, stable voltage can be supplied to each CPU, even if the upper and lower loads are different or a battery is being used. The LDOs improve the margin of collection in the tank capacitor or task schedule operation, and power efficiency is raised even further. The circuit can be implemented on silicon without a large external control circuit and inductor such as a switching regulator. This circuit was applied to an in-vehicle lock-step system because the upper and lower loads and tasks are the same. Additionally, by using the proposed task scheduling to maximize efficiency, this circuit can be applied not only to lock-step systems but also to general systems. Test chips were fabricated using 90-nm standard CMOS technology. Although the maximum power efficiency of a conventional circuit with a simple LDO is 44.4%, efficiency of the proposed charge-recycling circuit turned out to be as high as 87.1% with the test chips.

F5: Low-power radios for sensor networks

Sensor node systems are expected to be a major growth field for semiconductor markets, and will connect to the cloud in a future cyber physical world. Wireless sensor networks (WSN) face multiple challenges from system design to low-power electronics and energy sources. Ultra-low-power radios are key elements in such systems, putting high demand on energy efficiency in different modes of operation (active, wake-up and sleep). This forum presents system perspectives and practical design aspects in various energy-efficient and short-range radio circuits and systems, including an introduction to various applications and their requirements for RF and digital signal processing in WSN systems. The technologies range from RF to digital signal processing and algorithms to give comprehensive understanding of recent advances. The forum begins with two high-level design talks on low power radio SoCs. The following four talks present ultra-low-power transceivers for body-area networks, sensor nodes, and health-monitoring applications. The last two talks cover efficient power management and emerging compression methodologies.

An accurate method for predicting temperature-dependent current mismatch in weak inversion region of long and wide channel MOSFET without subthreshold hump

We have found and verified that the current mismatch σ(ΔI/I) in the weak inversion region can be accurately predicted on the basis of the transconductance efficiency gm/I when a MOSFET does not have a subthreshold hump. We have also verified that, in a relatively long and wide channel MOSFET, the value of gate-voltage mismatch σ(ΔI/gm)(LW)1/2 in the weak inversion region converges to a constant value, regardless of the channel size and temperature. The constant value is determined by the MOSFET structure. In our method, both the convergence value of σ(ΔI/gm)(LW)1/2 in the weak inversion region and the gm/I behavior are used as input information of the σ(ΔI/I) prediction. It is possible to take this constant convergence value as an approximate value of σ(ΔI/gm)(LW)1/2, also in the moderate inversion region. Using this value, our method of σ(ΔI/I) prediction can be applied to the moderate inversion region with a reasonable degree of accuracy. In addition, a method for improving the accuracy of the predictions in the strong inversion region will be presented. We will discuss the mechanism that causes the value of σ(ΔI/gm)(LW)1/2 in the weak inversion region to become a constant value. On the other hand, when a MOSFET has a subthreshold hump, the constant value approximation of σ(ΔI/gm)(LW)1/2 in the weak inversion region cannot be used. The value of σ(ΔI/gm)(LW)1/2 in weak and moderate inversion regions increases with a decrease in current. This increase randomly fluctuates depending on the wafer or temperature. As a result, to predict the current mismatch σ(ΔI/I) accurately, it is necessary to remove the subthreshold hump of a MOSFET completely.

Green semiconductor technology with ultra-low power on-chip charge-recycling power circuit and system

For low power consumption which makes more than doubles a battery life, the charge-recycling system by reuse the energy between the two or more CPUs and the task scheduling technique for high efficiency are proposed. In this architecture, CPUs are divided into upper and lower load groups, and electrical charges are shared among the stacked CPUs and a tank capacitor. To control divided loads, a high speed and efficient regulator are needed. The internal circuit voltage variation between upper and lower modules is solved by seven LDO regulators, boosting switched capacitor and the tank capacitor. As a result, the stable voltage can be supplied to each CPU, even if upper and lower loads are different or battery is used. The LDOs improve the margin of accumulation of tank capacitor or task schedule operation, and the power efficiency is raised further. The system can be on-chip without external large control circuit and inductor like switching regulator. The test chips were fabricated using 90nm standard CMOS technology. Although the power efficiency of the conventional system with a simple LDO is 44.4% at the maximum, that of the proposed charge-recycling system improves to 88.9%.

New Type of Nb Microbridges

Fabrication procedure using microfabrication technology and DC characteristics of new type of Nb microbridges are presented. The bridges have a threedimensional rotationally symmetric structure which connects two Nb planes separated by a thin SiO2 film through a small pinhole in the SiO2 film. The bridges exhibit no hysteresis in the current-voltage characteristics and the critical current varied weakly with a temperature. Two-junction SQUIDs composed of the present bridges show a periodic dependence of the critical current (Ic) on an applied magnetic field at a temperature where Ic almost saturates with a temperature. These are important improvement over one or two-dimensional microbridges.

Tool Support for Consistency Verification of UML Diagrams

Manual verification of the consistency between UML state machine diagrams and sequence diagrams is labor-intensive and prone to make mistakes. We provide an automatic tool written in Java that performs the verification by translating UML diagrams into a process description of CSP(_M) language. The tool takes in a PlantUML file and verifies the consistency with a model-checker FDR.

A Serial Booth Multiplier Using Ring Oscillator

An increase of half-hearing person caused by progressive aging of society in our country leads to an increase in demand for a digital hearing aid with a DSP. Because of a hard physical limit for battery capacity which stems from its wearing form, the battery life of an existing digital hearing aid comes up to only about few days. In this paper, we proposed an implementation for a bit-serial multiplier for DSP in a hearing aid with high working frequency and low power consumption. To reduce the power consumption associated with clock generation, we use a ring oscillator to dynamically generate clock pulse only in the period of calculation. In addition, we adopt the Booth encoding to reduce the number of partial products in multiplication and reduce the calculation time and power consumption associated with it. We implement the proposed multiplier and show the effectiveness of it through the comparison experiments.

3D 2 processing architecture — High reliability and low power computing for novel nano tactile sensor array

We have proposed new instrumental techniques to quantify human touch feelings by nano tactile sensor array system with 3D2 processing architecture. In the computation of quantification of human touch feelings, high-level semantics features are calculated from low-level features which are the result of FFT, wavelet translation, etc. For some application, especially medical application, high reliability is required for the recognition results. Furthermore, real-time processing and low power computing are also required. 3D2 Processing architecture provides high reliable and low power computing for the accelerator. The architecture has three features: Parallel Computation of Multiple Recognition Algorithms for High Reliability, Spatial-Parallel Temporal-Pipeline Streaming Processing for High Energy Efficiency Processing, and Current Reuse Energy Pipeline for Low Power Processing.

A battery operated normally-off computing technique for energy efficient sensor node applications

A Normally Off (Noff) Computing technique to get the higher energy efficiency and low power dissipation are remarkable technique for the both high performance computing and and the embedded computing. The Noff computing with DC power supply has been studied but there are no research about the Noff computing with battery operation for sensor network applications. This paper described the optimization of the battery operated Noff computing sensor node application. The battery life time characterization affected by the various current flow operation modes which had been reported. We analyze the theory of the battery life time and provide the battery life time estimation tool based on the theory and measured data of chemical battery. By combining the above tool and the Noff computing controlling method, we can get the optimized energy efficient managements for sensor node application.

Bounded model checking of Time Petri Nets using SAT solver

To carry out performance evaluation of an asynchronous system, the system is modeled as Time Petri Net (TPN) and an iteration of Petri net simulations produces its performance index. The TPN model needs to satisfy required properties such as deadlock freeness. We proposed a symbolic representation of TPN for SAT-based bounded model checking. In the proposed encoding scheme, firing of transitions and elapsing of place delays are expressed as boolean formulas discretely. Our representation can work with relaxed ∃-step semantics which enables to perform each step by two or more transitions. We applied the encoding to example TPN models and checked the deadlock freeness using SAT solver. The results of experiments demonstrated the effectiveness of the proposed representation.