Fukashi Morishita

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

For future ULSI DRAMs beyond the 256 Mb generation, several circuit techniques and memory cell structures have been proposed to meet the requirement of high performance at low voltage. These solutions frequently involve complicated processing steps and/or the ultimate limitations of current Si-MOS devices. DRAM on silicon on insulator (SOI) substrate is a more simple solution to the problem. Thin-film SOI structures with isolation by implanted oxygen (SIMOX) process are under investigation for SRAM and logic. A SOI-DRAM test device with 100 nm thick SOI film has been fabricated in 0.5 /spl mu/m CMOS/SIMOX technology. With this 64 kb SOI-DRAM the bit-line to memory cell capacitance ratio Cb/Cs is reduced by 25% compared with the reference bulk-Si DRAM, because of the decreased junction capacitance. RAS access time tRAC is 70 ns at 2.7 VVcc, as fast as the equivalent bulk-Si device at 4 VVcc. The clock timing in this DRAM is not optimized, so access time should improve with well-tuned clocks. The boosted-level generator with body-contact structure enhances the upper Vcc margin and the reduced body-effect of sense-amplifier transistors improves the lower Vcc margin. The SOI-DRAM has an operating Vcc range from 2.3 V to 4.0 V. >

Approaches to extra low voltage DRAM operation by SOI-DRAM

The newly designed scheme for a low-voltage 16 MDRAM/SOI has been successfully realized and the functional DRAM operation has been obtained at very low supply voltage below 1 V. The key process and circuit technologies for low-voltage/high-speed SOI-DRAM will be described here. The extra low voltage DRAM technologies are composed of the modified MESA isolation without parasitic MOS operation, the dual gate SOI-MOSFETs with tied or floating bodies optimized for DRAM specific circuits, the conventional stacked capacitor with increased capacitance by thinner dielectric film, and the other bulk-Si compatible DRAM structure. Moreover, a body bias control technique was applied for body-tied MOSFETs to realize high performance even at low voltage. Integrating the above technologies in the newly designed 0.5-/spl mu/m 16 MDRAM, high-speed DRAM operation of less than 50 ns has been obtained at low supply voltage of 1 V.