Junji Senzaki

Effect of gate oxidation method on electrical properties of metal-oxide-semiconductor field-effect transistors fabricated on 4H-SiC C(0001̄) face

The effect of gate oxidation method on the electrical properties of metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated on 4H-SiC C(0001) face has been investigated. In the case of SiC MOSFETs fabricated by dry gate oxidation, the peak value of field-effect mobility (μFE) is 16.3 cm2/V s. On the other hand, pyrogenic gate oxidation and pyrogenic gate oxidation followed by H2 postoxidation annealing (POA) considerably decreased the interface trap density (Dit) and the threshold voltage, and markedly improved the μFE. The depth profiles of hydrogen density were measured using secondary ion mass spectroscopy. These verified that pyrogenic gate oxidation increases hydrogen density at the SiO2/SiC interface compared to dry gate oxidation, and that the pyrogenic gate oxidation followed by H2 POA increases considerably it. It is thought that the Dit reduction might be caused by the passivation of interface states by –H or –OH. The peak value of μFE for SiC MOSFETs fabricated by pyrogenic gat...

Excellent effects of hydrogen postoxidation annealing on inversion channel mobility of 4H-SiC MOSFET fabricated on (11 2 0) face

Effects of hydrogen postoxidation annealing (H/sub 2/ POA) on 4H-silicon carbide (SiC) MOSFETs with wet gate oxide on the (112~0) face have been investigated. As a result, an inversion channel mobility of 110 cm/sup 2//Vs was successfully achieved using H/sub 2/ POA at 800/spl deg/C for 30 min. H/sub 2/ POA reduces the interface trap density by about one order of magnitude compared with that without H/sub 2/ POA, resulting in considerable improvement of the inversion channel mobility to 3.5 times higher than that without H/sub 2/ POA. In addition, 4H-SiC MOSFET with H/sub 2/ POA has a lower threshold voltage of 3.1 V and a wide gate voltage operation range in which the inversion channel mobility is more than 100 cm/sup 2//Vs.

High channel mobility in normally-off 4H-SiC buried channel MOSFETs

We have fabricated buried channel (BC) MOSFETs with a thermally grown gate oxide in 4H-SiC. The gate oxide was prepared by dry oxidation with wet reoxidation. The BC region was formed by nitrogen ion implantation at room temperature followed by annealing at 1500/spl deg/C. The optimum doping depth of the BC region has been investigated. For a nitrogen concentration of 1/spl times/10/sup 17/ cm/sup -3/, the optimum depth was found to be 0.2 /spl mu/m. Under this condition, a channel mobility of 140 cm/sup 2//Vs was achieved with a threshold voltage of 0.3 V. This channel mobility is the highest reported so far for a normally-off 4H-SiC MOSFET with a thermally grown gate oxide.

Strong dependence of the inversion mobility of 4H and 6H SiC(0001) MOSFETs on the water content in pyrogenic re-oxidation annealing

The inversion channel mobility of 4H and 6H-SiC(0001) metal-oxide-semiconductor field-effect transistors (MOSFETs) has been evaluated for its dependence on the re-oxidation annealing (ROA) conditions in a wet oxidizing ambient. The wet ambient was supplied by the pyrogenic reaction of hydrogen and oxygen gas (pyrogenic ROA), where the water vapor content (/spl rho/(H/sub 2/O)) was controlled by adjusting the hydrogen/oxygen gas flow rate. Not only the annealing temperature and the time, but also /spl rho/(H/sub 2/O) are found to be the critical parameters for improving channel mobility. As a result, field-effect channel mobilities as high as 47 cm/sup 2//Vs for 4H and 95 cm/sup 2//Vs for 6H-SiC MOSFETs were achieved by pryrogenic ROA treatment with a /spl rho/(H/sub 2/O) of 50%.

Correlation between reliability of thermal oxides and dislocations in n-type 4H-SiC epitaxial wafers

The correlation between thermal oxide reliability and dislocations in n-type 4H-SiC (0001) epitaxial wafers has been investigated. The thermal oxides were grown by dry oxidation at 1200°C followed by nitrogen postoxidation annealing. Charge-to-breakdown values of thermal oxides decrease with an increase in the number of the dislocations in a gate-oxide-forming area. Two types of dielectric breakdown modes, edge breakdown and dislocation-related breakdown, were confirmed by Nomarski microscopy. In addition, it is revealed that basal plane dislocation is the most common cause of the dislocation-related breakdown mode.

Correlation between channel mobility and shallow interface traps in SiC metal–oxide–semiconductor field-effect transistors

The shallow interface trap density near the conduction band in silicon carbide (SiC) metal–oxide–semiconductor (MOS) structure was evaluated by making capacitance–voltage measurements with gate-controlled-diode configuration using the n-channel MOS field effect transistors (MOSFETs). The close correlation between the channel mobility and the shallow interface trap density was clearly found for the 4H- and 6H-SiC MOSFETs prepared with various gate-oxidation procedures. This result is strong evidence that a significant cause of the poor inversion channel mobility of SiC MOSFETs is the high density of shallow traps between the conduction band edge and the surface Fermi level at the threshold.

Characterization of Pb(Zr, Ti)O3 Thin Films on Si Substrates Using MgO Intermediate Layer for Metal/Ferroelectric/Insulator/Semiconductor Field Effect Transistor Devices

Pb(Zr, Ti)O3(PZT)/MgO/Si(001) stacked structures, one of the potential components of ferroelectric-gate field effect trnsistors, have been fabricated and characterized. According to the electrical characterization of MgO/Si structures, MgO thin films prepared on Si substrates at a low growth rate showed a small leakage current of ~10-8 A/cm2 order in an electric field of 1 MV/cm. In C-V measurements of as-grown MgO/Si interfaces, injection-type hysteresis was observed because of crystal defects in the MgO film adjacent to the interface. After oxygen annealing at 400°C, however, it showed no hysteresis and a low interface trap density of the order of 1011 cm-2eV-1 was achieved with no formation of a low-dielectric layer at the MgO/Si interface. These results indicate that MgO thin films are applicable as gate insulators of FETs. After a PZT film was deposited on the MgO/Si structure, the C-V characteristic of the stacked structure showed a ferroelectric hysteresis curve and a low interface trap density of 5×1011 cm-2eV-1. A maximum memory window width of 1.2 V was obtained for the PZT thin film on Si substrate with a MgO intermediate layer.

Relationship between channel mobility and interface state density in SiC metal–oxide–semiconductor field-effect transistor

Temperature dependence of threshold voltage in n-channel SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) was studied. Linear relation was observed between the threshold voltage shift when the temperature varies from −150 to 150 °C and the number of the interface states present within the energy range of 0.2–0.4 eV from the conduction band edge energy Ec. This relationship revealed that the interface state profile near Ec in n-channel SiC MOSFETs can be represented by that in n-type SiC MOS capacitors. The relationship between the channel mobility and the interface state profile also suggested that the interface states within the energy range of 0.2–0.4 eV from Ec have little influence on the channel mobility.

Deep ultraviolet Raman scattering characterization of ion-implanted SiC crystals

Multiple energy phosphorous ions were implanted into 4H-SiC at room temperature and at an elevated temperature (500 °C) followed by annealing at various temperatures. Deep ultraviolet Raman microscopy was used to analyze the effect of the implantation dose and postannealing temperature on the recovery of surface layers damaged by the implantation. The Raman analysis showed that the recovery rate of the crystallinity increased with an increase in the annealing temperature. However, for highly dosed samples, recovery was not complete even with annealing temperatures up to 1700 °C. With room-temperature implantation, part of the implanted layer was converted into a 3C structure with heavy stacking faults. New Raman bands were observed at below 500cm−1 in samples heavily dosed with 4.0×1016cm−2 after annealing, which revealed that excess phosphorus precipitates. A downshift of the phonon Raman bands and a reduction in the LO–TO-phonon frequency splitting were observed in as-implanted samples and ones that are...

Effects of interface state density on 4H-SiC n-channel field-effect mobility

We investigated the effects of D IT at the interface between SiO2 and Si-, C-, and a-face 4H-SiC in n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) that were subjected to dry/nitridation and pyrogenic/hydrotreatment processes. D IT at E C − E T = 0.2 eV was evaluated by the C − ψ S method using MOS capacitors and was accurately reflected in the subthreshold slope of the MOSFETs. The peak field-effect mobility was inversely proportional to D IT. The mobility for the a-face MOSFETs was 1.5 times or more higher than the other faces mobilities, indicating that mobility limiting factors other than D IT(0.2 eV) may exist for the Si- and C-face interfaces.