Kazutoshi Tsuda

Novel fractional-N PLL frequency synthesizer with reduced phase error

Conventionally, the division ratio of the programmable divider in the Phase Locked Loop (PLL) frequency synthesizer is an only integer. Therefore, it has been hoped to realize the fractional-N programmable divider which can divide not only an integer step but also a fractional step. In this paper, a new fractional-N programmable divider for the PLL frequency synthesizer is proposed. In this divider, the width of phase error pulse which phase detector produces in every period of reference frequency is decreased by introducing the new division ratio (N+1/2) besides N and (N+1).

Fast Settling PLL Frequency Synthesizer Utilizing The Frequency Detector Method Speedup Circuit

We propose two items for the fast frequency settling in the phase locked loop (PLL) frequency synthesizer. One is a PLL frequency synthesizer utilizing a frequency detector method speedup circuit (FDMSC). From the experimental results, it is observed that fast frequency settling can be achieved. The other is a shortcut lowpass filter (LPF) method with the FDMSC in the PLL frequency synthesizer. The frequency settling time has been speeded up further by changing the time constant of the LPF to a smaller value only in the rising condition.

A New Fractional-N PLL Frequency Synthesizer

Recently, the speedup of lock up time is required in the Phase Locked Loop (PLL) frequency synthesizer. The fractional-N method is one of the most important techniques among the speedup methods proposed hitherto. The fractional-N programmable divider can divide not only an integer step but also a fractional one. However, the phase detector always generates the phase error pulse in every period of reference frequency and the elimination of this phase error pulse seems to be difficult. In this paper, a new fractional-N programmable divider is proposed. In this divider, the width of phase error pulse is decreased by introducing the new division ratio (N + 1/2) besides N and (N + 1). Then, the width of maximum phase error pulse in the new fractional-N programmable divider is less than or equal to half of that of the conventional one.