Kouichi Syoubu

Novel fractional-N PLL frequency synthesizer with reduced phase error

Conventionally, the division ratio of the programmable divider in the Phase Locked Loop (PLL) frequency synthesizer is an only integer. Therefore, it has been hoped to realize the fractional-N programmable divider which can divide not only an integer step but also a fractional step. In this paper, a new fractional-N programmable divider for the PLL frequency synthesizer is proposed. In this divider, the width of phase error pulse which phase detector produces in every period of reference frequency is decreased by introducing the new division ratio (N+1/2) besides N and (N+1).

Fast Settling PLL Frequency Synthesizer Utilizing The Frequency Detector Method Speedup Circuit

We propose two items for the fast frequency settling in the phase locked loop (PLL) frequency synthesizer. One is a PLL frequency synthesizer utilizing a frequency detector method speedup circuit (FDMSC). From the experimental results, it is observed that fast frequency settling can be achieved. The other is a shortcut lowpass filter (LPF) method with the FDMSC in the PLL frequency synthesizer. The frequency settling time has been speeded up further by changing the time constant of the LPF to a smaller value only in the rising condition.

A new PLL frequency synthesizer using multi-programmable divider

In this paper, we propose a new phase locked loop (PLL) frequency synthesizer utilizing the multiprogrammable divider which can attain a higher speed lock-up time by increasing the loop gain. The effectiveness of the PLL frequency synthesizer with the multiprogrammable divider are shown by theoretical considerations and experimental results.

A digital signal processing type frequency locked loop for frequency shift keying demodulation

In this paper, we propose a digital signal processing type frequency locked loop (DSP-FLL) using a frequency difference detector (FDD). Since the DSP-FLL is controlled by the frequency, the pole of the voltage controlled oscillator vanishes in the baseband equivalent circuit. Therefore, the transfer function becomes first order and a ringing does not occur. Furthermore, it can be understood from the detection property of the FDD that a cycle slip does not occur and the DSP-FLL can pull in the frequency step input up to half of the sampling frequency.

A Novel (N + 1/2) Pulse Swallow Programmable Divider for the Prescaler PLL Frequency Synthesizer

AbstractIn this paper, we propose a new speedup method of frequency switching time of the prescaler PLL frequency synthesizer using

Dual loop DSP-PLL with wide frequency acquisition range and fast frequency acquisition

(N + \tfrac{1}{2})

PLL Frequency Synthesizer with Multi-Phase Detector

pulse swallow programmable divider. The