Keisuke Kaneko
Panasonic
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Publication
Featured researches published by Keisuke Kaneko.
symposium on vlsi circuits | 2007
Masaitsu Nakajima; Takao Yamamoto; Masayuki Yamasaki; Keisuke Kaneko; Tetsu Hosoki
We propose a novel dual-processor core which adopts a shared L1 cache with active way scheme. In this scheme, each WAY of cache is owned by specific processor and replace operation is only happened to its own WAYs. This architecture only requires dual port TAG, and no dual port DATA memory to realize simultaneous access from both processors, and can guarantee no cache thrashing and no snoop overhead. And also by sharing cache memory and cache controller, power dissipation is 23% smaller in case of heavy load and area is 29 % smaller than dual processor core with snoop cache.
Archive | 2008
Keisuke Kaneko; Takao Yamamoto; Masayuki Yamasaki; Nobuo Higaki; Kazushi Kurata; Ryuta Nakanishi
Archive | 2004
Tetsuya Tanaka; Hazuki Okabayashi; Ryuta Nakanishi; Tokuzo Kiyohara; Takao Yamamoto; Keisuke Kaneko
Archive | 2006
Hazuki Okabayashi; Tetsuya Tanaka; Ryuta Nakanishi; Masaitsu Nakajima; Keisuke Kaneko
Archive | 2006
Keisuke Kaneko
Archive | 1998
Keisuke Kaneko; Shinji Ozaki; 伸治 尾崎; 圭介 金子
Archive | 2000
Keisuke Kaneko; Tetsuya Tanaka; 哲也 田中; 圭介 金子
Archive | 1998
Toru Morikawa; Nobuo Higaki; Shinji Ozaki; Keisuke Kaneko; Satoshi Ogura; Masato Suzuki
Archive | 2002
Keisuke Kaneko
Archive | 2006
Takao Yamamoto; Tetsuya Tanaka; Ryuta Nakanishi; Masaitsu Nakajima; Keisuke Kaneko; Hazuki Okabayashi
