Keitaro Sekine

Low voltage four-quadrant analog multiplier using square-root circuit based on CMOS pair

We proposed a square-root circuit based on CMOS pairs. In this paper, we propose a low voltage four-quadrant analog multiplier using the square-root circuit. Also we confirmed this operation by PSpice simulations.

A CMOS Analog Multiplier Free from Mobility Reduction and Body Effect

This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. Their gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 Vp-p input signal at 2.5 V supply voltage, and that the 3 dB bandwidth is up to about 13.3 MHz.

A synthesis of a novel current-mode operational amplifier

In this letter, a novel current-mode operational amplifier (COA) is proposed. The proposed COA can operate at 2 V (±1 V) supply voltage. For high frequency operation it has only an npn transistor in signal path. Finally, SPICE simulation are shown to verify the performance of the proposed COA.

A 1-MHz 7th-order continuous-time lowpass filter using very low distortion CMOS OTAs

In this paper, a 1-MHz 7th-order Butterworth lowpass filter is designed. The filter is composed of very low distortion CMOS OTAs. The linearity of the OTA is free from mobility reduction and body effect. This is the reason that the OTA shows low distortion characteristics. Thus, the lowpass filter also has low distortion. We confirmed that the filter exhibited very low distortion by simulation. When an input signal with 1 V (peak-peak) and 333 kHz is applied, THD of the lowpass filter becomes only 0.094%.

A novel CMOS OTA free from mobility reduction effect

Distortion of OTAs is caused by nonideal factors such as the mobility reduction effect, channel length medulation, transistor mismatch and so on. The transfer function of the proposed OTA is free from the mobility reduction effect. Thus, the proposed OTA is expected to have better linearity than conventional OTAs.

A Low Power Dissipation Technique for a Low Voltage OTA

This paper proposes a novel low power dissipation technique for a low voltage OTA. A conventional low power OTA with a class AB input stage is not suitable for a low voltage operation (±1.5 V supply voltages), because it uses composite transistors (referred to CMOS pair) which has a large threshold voltage. On the other hand, the tail-current type OTA needs a large tail-current value to obtain a sufficient input range at the expense of power dissipation. Therefore, the conventional tail-current type OTA has a trade-off between the input range and the power dissipation to the tail-current value. The trade-off can be eliminated by the proposed technique. The technique exploits negative feedback control including a current amplifier and a minimum current selecting circuit. The proposed technique was used on Wangs OTA to create another OTA, named Low Power Wangs OTA. Also, SPICE simulations are used to verify the efficiency of Low Power Wangs OTA. Although the static power of Low Power Wangs OTA is 122 μW, it has a sufficient input range, whereas conventional Wangs OTA needs 703 μW to obtain a sufficient input range. However, we can say that as the input signal gets larger, the power of Low Power Wangs OTA becomes larger.

LV/LP CMOS high speed analog multiplier

In this paper we propose a new LV/LP four quadrant analog multiplier. The multiplier is composed of a LV/LP CMOS composite cell with two high input impedance terminals (LVLPCCC) which has a square-law current-voltage characteristic. SPICE simulation results using MOSIS 2 /spl mu/m n-well process parameters show that the multiplier achieves a maximum differential input voltage of 2V/sub pp/, f/sub -3 dB/ of 250 MHz and power consumption of 1.17 mW with a 3 V supply. Also, simulated Total Harmonic Distortion (THD) less than 1% at frequency up to 8 MHz for 2 V/sub pp/ input voltage is obtained.

Low-power ASK receiver circuit for wireless communication system

In this paper, we propose low-power receiver circuits for a wireless communication system using an ASK signal. The circuit structures are is suitable for low supply current. The proposed circuits are designed and simulated by Spectre using 0.8 /spl mu/m CMOS process parameters, and operates with a supply current below 1 /spl mu/A.

LV/LP CMOS square-law circuits

In this paper several new CMOS square-law circuit cells with two high impedance input terminals are proposed to achieve wide input voltage operating range with low supply voltage. These cells are constructed based on two methods introduced and as a result, highly accurate signal processing with low power dissipation is possible. The simulations and/or measurements carried out using MOSIS 2 /spl mu/m n-well process have shown that one of the cells based on the adaptive bias technique, one of the methods introduced, achieved /spl omega//sub 3dB/ of 426 MHz and the input voltage operating range of 1.8 V with a 3 V supply.

A High Impedance Current Source Using Active Resistor

This paper presents a novel method to increase an impedance of a current source. The proposed circuit with a cascode and gain-boosting configuration is also presented. The operation has been confirmed by simulation using a 0.18 μm CMOS technology.