Akira Hyogo

Balanced Three-Phase Active-RC Tow-Thomas Biquad Complex Filter for Wireless Communication Systems

A three-phase complex filter for a balanced three-phase analog signal processing is proposed. The proposed three-phase active-RC Tow-Thomas biquad complex filter can reduce total resistance by 10 percent, total capacitance by 25 percent, and power consumption by 22 percent compared to a conventional fully differential quadrature complex one.

A low voltage OTA using MOSFET in the triode region and cascode current mirror

This paper presents a simple, low voltage CMOS OTA circuit based on two voltage buffer circuits. The simulated results of the proposed circuit with 0.18 /spl mu/m CMOS technology show that it can operate with 1.2V supply voltage, and in less than 0.1% THD for 100kHz, 600mV peak-to-peak differential input signal voltage.

Signal-to-noise ratio improvement of common-gate CMOS LNA for Ultra-Wide-Band

This paper proposes a circuit structure which can improve signal-to-noise ratio of a conventional common-gate CMOS LNA for UWB (Ultra-Wide-Band; 3.1-10.6 GHz) using 0.18 um CMOS technology. The simulated results show that the proposed circuit has gain of 16.3-18.8 dB and NF of less than 3dB as well as good compatibility with input matching in a wide frequency range needed in UWB, and it consumes 16.2 mW with a 1.2 V supply voltage.

A low-distortion two-path fourth-order bandpass delta-sigma modulator using horizontal opamp sharing

In this paper, a low-distortion two-path fourth-order bandpass DeltaSigma modulator which has only two opamps is proposed. The proposed modulator is based on both horizontal opamp sharing technique and feedforward topology. It achieves SNDR(signal-to-noise plus distortion ratio) of 80.14 dB and DR (dynamic range) of 82 dB over 200 kHz signal bandwidth centered at 10.03 MHz.

Input-Feedforward Two-Path Band-Pass Delta-Sigma Modulator Based on Horizontal or Vertical Opamp Sharing Technique

In this paper, horizontal (where an opamp is shared in two adjacent stages) and vertical (where an opamp is shared across two paths) opamp sharing techniques for a two-path band-pass (BP) Δ Σ modulator are described, and input-feedforward two-path fourth-order BP Δ Σ modulators that have only two opamps are proposed. The proposed modulators are based on the horizontal or vertical opamp sharing technique. They can be realized with both a summation circuit using a switched capacitor (SC) network and a second-order high-pass filter (HPF) with a horizontal shared opamp or a double-sampling first-order HPF with a vertical shared opamp, which are based on an SC first-order HPF with an opamp. These techniques can reduce the number of opamps with no additional component and the chip area as well as realize lower power consumption.

Non-binary cyclic and binary SAR hybrid ADC

We propose a hybrid A/D converter consist of non-binary or beta-weighted cyclic ADC, and binary SAR ADC. The upper bits or MSBs are converted by beta-weighted cyclic ADC. With the help of automatic beta-value estimation, MSBs are converted accurately. One of the capacitors of the cyclic ADC is composed by a binary weighted capacitor array. After MSB conversion, residual voltage of cyclic ADC remains on the capacitor array. Lower bits or LSBs are determined using this capacitor array by Successive Approximation (SAR-) algorithm. Beta-weighted cyclic brings high accuracy to the ADC, and lower bit SAR-ADC helps to improve conversion speed and to reduce power consumption.

A 5Gb/s adaptive equalizer using filter switching

This paper presents an adaptive equalizer circuit using filter switching for 5 Gb/s data communication over electrical backplane. Most of conventional equalizers are based on amplification of high frequency component of the received signal, and the performance degrades when the line is very short and the attenuation is small. The proposed one solves this issue by using two signal paths, high-pass and low-pass path, and switching them based on the received signal. It can compensate 5 Gb/s PRBS through FR4 backplane in 0 cm, 25 cm, 50 cm and 75 cm long both with and without pre-emphasis.

A High-Q Active Inductor Circuit for Quasi-Millimeter-Wave Frequency Range

This paper describes a novel high-Q active inductor circuit configuration composed of an operational transconductance amplifier (OTA) and an input RC network. Due to the phase rotation made by the input RC network, the active inductor circuit provides high-Q inductive impedance at higher frequencies. According to circuit simulation with design-kit of a 90-GHz-fT SiGe HBT technology, an inductance of more than 0.53nH and Q of more than 80 can be obtained at quasi-millimeter-wave frequency, 24GHz. The Q value is tunable by controlling the transconductance of the OTA. These features are also ensured by means of measurements of fabricated active inductor circuit. Since the active inductor circuit needs small chip area, which is 25% of a conventional passive inductor, the proposed active inductor contributes to implement a cost-effective high-Q notch filter for frequencies up to quasi-millimeter-wave frequencies.

3-phase active-RC Tow-Thomas biquad complex filter

Quadrature signal system, which has an I-channel and a Q-channel, is widely used in analog baseband signal processing for wireless communication system. This sort of system needs a four-phase signal consisting of I-positive, expositive, I-negative, and Q-negative, so it needs a large area. A balanced three-phase analog signal processing has been proposed, and this system can realize an equivalent functionality to the fully-balanced system in smaller chip area. In this paper, a three-phase complex filter is proposed. The proposed circuit can reduce total resistance by 10%, total capacitance by 25%, and power consumption by 22% compared with four-phase conventional one.

A Design Approach for Low Phase Noise 5GHz Complementary Quadrature Oscillator

A novel complementary quadrature LC oscillator is presented for achieving lower phase noise. One proposed and three conventional structures, designed in a 0.18 mum CMOS technology, are simulated in both the triple-well and the twin-well (exactly the quasi twin-well) process technologies and each phase noise is compared. These circuits operate at 5 GHz and draw 8.6 mA from a 1.8 V supply. In the triple-well environment 1-4 dBc/Hz over the entire offset frequency is improved, for the twin-well 2-5 dBc/Hz. The best-case, the proposed circuit in the triple-well, the phase noise is -130.0 dBc/Hz at 1 MHz offset frequency.