Keitarou Kondou

Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry

This paper presents a 60-GHz direct-conversion RF front-end and baseband transceiver including analog and digital circuitry for PHY functions. The 65-nm CMOS front-end consumes 319 and 223 mW in transmitting and receiving mode, respectively. It is capable of more than 7-Gb/s 16QAM wireless communication for every channel of the 60-GHz standards, which can be extended up to 10 Gb/s. The 40-nm CMOS baseband including analog, digital, and I/O consumes 196 and 427 mW for 16QAM in transmitting and receiving modes, respectively. In the analog baseband, a 5-b 2304-MS/s ADC consumes 12 mW, and a 6-b 3456-MS/s DAC consumes 11 mW. In the digital baseband integrating all PHY functions, a (1440, 1344) LDPC decoder consumes 74 mW with the low energy efficiency of 11.8 pJ/b. The entire system including both RF and BB using a 6-dBi antenna built in the organic package can transmit 3.1 Gb/s over 1.8 m in QPSK and 6.3 Gb/s over 0.05 m in 16QAM.

A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry

This paper presents a 60 GHz direct-conversion front-end and baseband transceiver, including analog and digital circuitry for the PHY functions. The 65 nm CMOS front-end consumes 319 mW and 223 mW in transmitting and receiving mode, respectively, and is capable of more than 7 Gb/s 16QAM wireless communication for every channel of the 60 GHz standards. The 40 nm CMOS baseband incorporating LDPC consumes 196 mW and 398 mW for 16QAM in transmitting and receiving mode, respectively. The entire system, using a 6dBi antenna built in an organic package, can transmit 3.1Gb/s over 1.8 m in QPSK and 6.3 Gb/s over 0.05 m in 16QAM.

A new parallel algorithm for full-digital phase-locked loop for high-throughput carrier and timing recovery systems

A parallel algorithm for a full-digital phase-locked loop for high-throughput adaptive carrier and timing recovery systems has been developed. The proposed algorithm separately estimates an initial phase and a period fluctuation for a sampled signal, whereas they are simultaneously estimated by conventional algorithms. The new algorithm increases the pull-in frequency range by 1.6 times and reduces the convergence time by 41 %, compared to those of conventional parallel algorithms. Hardware for a carrier and timing recovery system utilizing interpolation with the maximum bit rate of 6.9 Gb/s was designed using 40 nm CMOS technology, resulting in a practical cell area of 0.081 µm2 for a 60 GHz millimeter-wave-based wireless communication application.

Uniform Latin square interleaving for correcting two-dimensional burst errors

A new class of Latin square, a uniform Latin square, as an interleaving algorithm has been introduced to correct two-dimensional (2-D) burst errors in data-storage systems. The uniform Latin square with order n=l/spl middot/m guarantees that there are no duplicated numbers in any (l-1)/spl times/m or l/spl times/(m-1) areas in an n/spl times/n square. Uniform Latin square interleaving has twice the error-correcting ability of the interleaving of a conventional Latin square for large 2-D burst errors.