Masaya Miyahara

A low-noise self-calibrating dynamic comparator for high-speed ADCs

This paper presents a low offset voltage, low noise dynamic latched comparator using a self-calibrating technique. The new calibration technique does not require any amplifiers for the offset voltage cancellation and quiescent current. It achieves low offset voltage of 1.69 mV at 1 sigma in low power consumption, while 13.7 mV is measured without calibration. Furthermore the proposed comparator requires only one phase clock while conventionally two phase clocks were required leading to relaxed clock. Moreover, a low input noise of 0.6 mV at 1 sigma, three times lower than the conventional one, is obtained. Prototype comparators are realized in 90 nm 10M1P CMOS technology. Experimental and simulated results show that the comparator achieves 1.69 mV offset at 250 MHz operating, while dissipating 40 muW/GHz ( 20 fJ/conv. ) from a 1.0 V supply.

Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry

This paper presents a 60-GHz direct-conversion RF front-end and baseband transceiver including analog and digital circuitry for PHY functions. The 65-nm CMOS front-end consumes 319 and 223 mW in transmitting and receiving mode, respectively. It is capable of more than 7-Gb/s 16QAM wireless communication for every channel of the 60-GHz standards, which can be extended up to 10 Gb/s. The 40-nm CMOS baseband including analog, digital, and I/O consumes 196 and 427 mW for 16QAM in transmitting and receiving modes, respectively. In the analog baseband, a 5-b 2304-MS/s ADC consumes 12 mW, and a 6-b 3456-MS/s DAC consumes 11 mW. In the digital baseband integrating all PHY functions, a (1440, 1344) LDPC decoder consumes 74 mW with the low energy efficiency of 11.8 pJ/b. The entire system including both RF and BB using a 6-dBi antenna built in the organic package can transmit 3.1 Gb/s over 1.8 m in QPSK and 6.3 Gb/s over 0.05 m in 16QAM.

A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry

This paper presents a 60 GHz direct-conversion front-end and baseband transceiver, including analog and digital circuitry for the PHY functions. The 65 nm CMOS front-end consumes 319 mW and 223 mW in transmitting and receiving mode, respectively, and is capable of more than 7 Gb/s 16QAM wireless communication for every channel of the 60 GHz standards. The 40 nm CMOS baseband incorporating LDPC consumes 196 mW and 398 mW for 16QAM in transmitting and receiving mode, respectively. The entire system, using a 6dBi antenna built in an organic package, can transmit 3.1Gb/s over 1.8 m in QPSK and 6.3 Gb/s over 0.05 m in 16QAM.

A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration

This paper presents a low-jitter, low-power and a small-area injection-locked all-digital PLL (IL-ADPLL). It consists of a dual-loop and a dual-VCO architecture in which one VCO (Replica) is placed in a TDC-less synthesizable ADFLL to provide continuous tracking of voltage and temperature variations. The other VCO (main) shares the control voltage with the replica VCO but is placed outside the loop and is injection-locked to lower its jitter and accurately set its frequency to the desired one. This approach avoids timing problems in the conventional ILPLL since the injection-locked VCO is placed outside the feedback loop. It also achieves a low power and a small area, due to the absence of a power hungry TDC and an area-consuming loop filter, while tracking any PVT variations. The IL-ADPLL is implemented in a 65 nm CMOS process and measurement results show that it achieves a 0.7ps RMS jitter at 1.2 GHz while having 1.6 mW and 0.97 mW power consumption with and without intermittent operation resulting in an FOM of -243 dB. It also consumes an area of only 0.022 mm2 resulting in the best performance-area trade-off system presented up-to-date.

A low-offset latched comparator using zero-static power dynamic offset cancellation technique

A low-offset latched comparator using new dynamic offset cancellation technique is proposed. The new technique achieves low offset voltage without pre-amplifier and quiescent current. Furthermore the overdrive voltage of the input transistor can be optimized to reduce the offset voltage of the comparator independent of the input common mode voltage. A prototype comparator has been fabricated in 90 nm 9M1P CMOS technology with 152 µm2. Experimental results show that the comparator achieves 3.8 mV offset at 1 sigma at 500 MHz operating, while dissipating 39 μW from a 1.2 V supply.

20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding

This paper presents a 64-QAM 60GHz CMOS transceiver, which achieves a TX-to-RX EVM of -26.3dB and can transmit 10.56Gb/s in all four channels defined in IEEE802.11ad/WiGig. By using a 4-bonded channel, 28.16Gb/s can be transmitted in 16QAM. The front-end consumes 251mW and 220mW from a 1.2-V supply in transmitting and receiving mode, respectively. Figure 20.3.1 shows the 60GHz direct-conversion front-end design. The transmitter consists of a 6-stage PA, differential preamplifiers, I/Q passive mixers and a quadrature injection-locked oscillator (QILO). The receiver consists of a 4-stage LNA, differential amplifiers, I/Q double-balanced mixers, a QILO, and baseband amplifiers. A direct-conversion architecture is employed for both TX and RX because of wide-bandwidth capability [1]. The LO consists of the 60GHz QILO and a 20GHz PLL. The 60GHz QILO works as a frequency tripler with the integrated 20GHz PLL. It can generate 7 carrier frequencies with a 36/40MHz reference, 58.32GHz(ch.1), 60.48GHz(ch.2), 62.64GHz(ch.3), and 64.80GHz(ch.4) defined in IEEE802.11ad/WiGig, 59.40GHz(ch.1-2), 61.56GHz(ch.2-3), and 63.72GHz(ch.3-4) for the channel bonding.

22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers

High-speed low-resolution ADCs are widely used for various applications, such as 60GHz receivers, serial links, and high-density disk drive systems. Flash architectures have the highest conversion rate without employing time interleaving. Moreover, flash architectures have the lowest latency, which is often required in feedback-loop systems. However, the area and power consumption are exponentially increased by increasing the resolution since the number of comparators must be 2N. A folding architecture is a well-known technique to reduce the number of comparators in an ADC while maintaining high sampling rate and low latency [1,2]. Folding architectures were previously realized by generating a number of zero crossings with folding amplifiers. However, the conventional folding amplifiers consume a large amount of power to realize a fast response. In contrast, a folding ADC with only dynamic power consumption and without using amplifiers is reported in [3]. However, only a folding factor of 2 is realized, and therefore the number of comparators is reduced by half.

A 0.022mm 2 970µW dual-loop injection-locked PLL with −243dB FOM using synthesizable all-digital PVT calibration circuits

For modern SoC systems, stringent requirements on on-chip clock generators include low area, low power consumption, environmental insensitivity, and the lowest possible jitter performance. Multiplying Delay-Locked Loop (MDLL) [1-2], subharmonically injection-locked techniques [3], and sub-sampling techniques [4-5] can significantly improve the random jitter characteristics of a clock generator. However, in order to guarantee their correct operation and optimal performance over process-voltage-temperature (PVT) variations, each method requires additional calibration circuits, which impose difficult-to-meet timing constraints. In the case of an injection-locked PLL (IL-PLL), a free-running frequency calibration is required. However, the output of an injection-locked oscillator is always fixed at the desired frequency, so a shift in the free-running frequency (e.g. caused by temperature and voltage variations) cannot be simply compensated for by using a frequency-locked loop (FLL). Therefore, we propose the use of a dual-loop topology with one free-running voltage-controlled oscillator (VCO) as a replica VCO placed inside a FLL for tracking temperature and voltage drift. The other VCO (the main VCO) is injection locked for producing a low-jitter clock, while the free-running frequency shift can be compensated for by the replica loop. The method provides robust output over temperature and voltage variations.

A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique

This paper presents a high-speed, low-power and wide signal swing differential dynamic amplifier using a common-mode voltage detection technique. The proposed dynamic amplifier achieves a 15.5 dB gain with less than 1 dB drop over a signal swing of 1.3 Vpp at an operating frequency of 1.5 GHz with a VDD of 1.2 V in 90 nm CMOS. The power consumption of the proposed circuit can be reduced linearly with operating frequency lowering.

A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC

This paper presents an opamp-free solution to implement noise shaping in a successive approximation register analog-to-digital convertor. The comparator noise, incomplete settling error of digital-to-analog convertor and mismatch are alleviated. Designed in a 65 nm CMOS technology, the prototype realizes 58 dB SNDR at 50 MS/s sampling frequency. It consumes 120.7 μW from a 0.8 V supply and achieves a FoM of 14.8 fJ per conversion step.