Keith R. Dimond

Design of an FPGA based adaptive neural controller for intelligent robot navigation

This article describes an alternative hardware solution to be implemented on FPGAs (field programmable gate array) for collision free robot navigation. A RAM based artificial neural network (ANN) was considered as the heart of the controller due to the advantage of its ease of implementation in conventional hardware. The structure of the ANN was well suited to realize the experiments for evolutionary robotics (ER). The hardware implementation gives massive parallelism of neural networks and the FPGA allows fast IC prototyping and low cost modifications.

Embedding a distributed evolutionary system into a population of autonomous mobile robots

This paper describes a fully embedded distributed evolutionary system that is able to achieve collision-free navigation in a few hundreds of trials. It reports the first experimental proof of the embedded evolution concept applied to the evolution of morphology and an unstructured control circuit of a population of six real robots in real time. Evolution selects the appropriate sensor configuration and speed levels that the robots should incorporate to perform specific tasks. The results show the influence of different mutation rates on the performance of the system. This work produced a genetic system where the population exists in a real environment.

An evolutionary controller for autonomous multi-robot systems

This article describes the implementation of a robot with an evolutionary control scheme, and experiments to examine evolutionary control with a population of five physical autonomous mobile robots. The control for the robots is totally embedded and performs collision-free behaviour. Both morphological features and the controller circuit are evolved. The robots constantly adapt to changes of surroundings by modifying their features and the weights of the RAM neural controller. The paper describes the evolutionary system and the results of experiments. These show that in relatively complex navigation tasks the proposed system evolves very quickly to develop a robust control system.

A Hardware Implementation of a Content Based Image Retrieval Algorithm

The need for efficient content-based image retrieval has increased tremendously in many application areas such as biomedicine, military, commerce, education, and Web image classification and searching. We present a method where local and global features are extracted. As a global feature, we extract the colour histogram. As local features, we extract prominent regions from the image using a k-means variant and a labeling algorithm. For each region, colour and spatial locations are extracted. Because these algorithms are computationally intensive, a hardware implementation is presented that accelerates the processing of the images. The proposed design is well suited for implementation on an FPGA. The device can be used as an add-on to a Personal Computer (PC).

A universal colour transformation architecture

Abstract A real-time transformation hardware for RGB to other colour models is presented here. Eight colour spaces, namely CMY , YIQ , HSV , HLS , CIEXYZ , CIExyY , CIELa * b * and YCrCb , have been tested for the system. Hardware results have then been compared against those generated by algorithmic implementations using floating point arithmetic for accuracy.

Hardware implementation of a genetic controller and effects of training on evolution

This article describes an FPGA (Field Programmable Gate Array) based hardware implementation of a genetic controller to be applied for the evolution of an Artificial Neural Network (ANN) [3] for collision-free navigation task of mobile robots. The adaptive nature of ANN enables it to train itself while the robot interacts with the environment. In addition to online training, the genetic evolution in neuron bits will be examined in an experiment to understand the interaction between evolution and lifetime adaptation of the ANN. The concept of chromosome for navigation task, design techniques of various blocks inside the GA controller will be elaborately described here.

A Stochastic Search Algorithm to Optimize an N-tuple Classifier by Selecting Its Inputs

The N-tuple method [4] is a statistical pattern recognition method, which decomposes a given pattern into several sets of n points, termed “N tuples”. The input connection mapping of the N-tuple classifier determines the sampling and defines the locations of the pattern matrix. Realizing the fact that the classification performance of the N-tuple classifier is highly dependant on the actual subset of the input bits probed [3][7], we have introduced an approach based on a Reward and Punishment (RnP) scheme to select input mappings of the classifier. We termed the classes with high error rates as critical classes. Different groups of tuples have been formed for different classes. The strategy was to employ more number of tuples to a critical class-group than an easily distinguishable class. In order to illustrate the capabilities of the RnP based measure the task of recognizing hand-written digits from NIST [10] database has been chosen.

A digital engineering curriculum with integrated, Windows-based EDA tools

The move to the Windows NT operating system by the University Computing Service, was an excellent opportunity for the Electronic Engineering Department at Kent to develop a new digital engineering curriculum, which closely integrated EDA tools and multi-media courseware into the syllabus. This paper examines the development of the curriculum and describes the software that has been integrated including tools for schematic capture, logic simulation, VLSI design and high-level simulation. The advantages of closely integrating computer based teaching with conventional lecture based material are described.

Realtime implementation of the viterbi decoding algorithm on a high-performance microprocessor

Abstract The complexity of the digital circuitry of the Viterbi decoder has prevented the algorithm from being fully exploited. One solution is to use a microprocessor to combat the complexity of the system. This paper presents a software implementation of the Viterbi algorithm on a high-performance microprocessor, for realtime decoding. The method implemented is based on forming a set of tables and using the internal structure of the processor for table manipulation rather than calculations. The paper gives a practical solution to the problem of memory management. The algorithm is reviewed mainly to define the necessary computational stages, with a detailed description of the software implementation of each stage. Also included is a comparison of the performance of the chosen processor with that of other processors, the results obtained showing a substantial improvement in performance over that of other microprocessor implementations published in the literature. This implementation would be suitable for low- and medium-speed data modems.

Realtime high resolution data acquisition unit for an MC68000 system

Abstract The general procedure for data acquisition in digital signal processing systems is to acquire a block of data and then analyse it. In a single-processor system, a considerable amount of data can be lost because, while data is being analysed by the processor, it is not sampled from the A/D converter. A dual-tasking machine has therefore been developed for continuous data analysis. The design requirements of the system are discussed. A block diagram of the system is presented, and the analogue-to-digital converter board is described in detail. The memory interchange board is also considered in depth.