Keith R. Milkove

Integration of self-assembled diblock copolymers for semiconductor capacitor fabrication

We combine a self-organizing diblock copolymer system with semiconductor processing to produce silicon capacitors with increased charge storage capacity over planar structures. Our process uses a diblock copolymer thin film as a mask for dry etching to roughen a silicon surface on a 30 nm length scale, which is well below photolithographic resolution limits. Electron microscopy correlates measured capacitance values with silicon etch depth, and the data agree well with a geometric estimate. This block copolymer nanotemplating process is compatible with standard semiconductor processing techniques and is scalable to large wafer dimensions.

High-capacity, self-assembled metal-oxide-semiconductor decoupling capacitors

We combine nanometer-scale polymer self assembly with advanced semiconductor microfabrication to produce metal-oxide-semiconductor (MOS) capacitors with accumulation capacitance more than 400% higher than planar devices of the same lateral area. The self assembly technique achieves this degree of enhancement using only standard processing techniques, thereby obviating additional process complexity. These devices are suitable for use as on-chip power supply decoupling capacitors, particularly in high-performance silicon-on-insulator technology.

High efficiency and low threshold current strained V‐groove quantum‐wire lasers

Multi‐quantum‐wire strained lasers are reported in the Ga1−xInxAs/Ga1−xAlxAs semiconductor material system with a minimum threshold current of 188 μA and maximum powers of ≊50 μW in continuous multimode operation at wavelengths of ≊980 nm and differential output of ≊0.5 μW/μA. The structures, fabricated by molecular‐beam epitaxy, are self‐aligned, self‐isolated, and minimize electrical and optical losses. Internal quantum efficiencies are ≊83% and internal losses are ≊4.2 cm−1. Characteristic temperatures of ≊260 K, and an increase in threshold current and lasing wavelength under externally applied stress changing from compressive to tensile conditions, show that the major determinants of lasing threshold are density of states and optical losses.

Two-level BEOL processing for rapid iteration in MRAM development

The implementation of magnetic random access memory (MRAM) hinges on complex magnetic film stacks and several critical steps in back-end-of-line (BEOL) processing. Although intended for use in conjunction with silicon CMOS front-end device drivers, MRAM performance is not limited by CMOS technology. We report here on a novel test site design and an associated thin-film process integration scheme which permit relatively inexpensive, rapid characterization of the critical elements in MRAM device fabrication. The test site design incorporates circuitry consistent with the use of a large-area planar base electrode to enable a processing scheme with only two photomask levels. The thin-film process integration scheme is a modification of standard BEOL processing to accommodate temperature-sensitive magnetic tunnel junctions (MTJs) and poor-shear-strength magnetic film interfaces. Completed test site wafers are testable with high-speed probing techniques, permitting characterization of large numbers of MTJs for statistically significant analyses. The approach described in this paper provides an inexpensive means for rapidly iterating on MRAM development alternatives to converage on an implementation suitable for a production environment.

Strain relaxation in silicon‐germanium microstructures observed by resonant tunneling spectroscopy

We have measured the resonant tunneling current–voltage I(V) characteristics of strained p‐Si/Si1−xGex double‐barrier microstructures ranging from 1.0 to 0.1 μm in lateral extent. The bias spacing between resonant current peaks in the I(V) reflects the energy separation of the Si1−xGex quantum well subbands, which is partially determined by the strain. As the lateral size of the structures decreases, we observe consistent shifts in the I(V) peak spacing corresponding to strain energy relaxation of ∼30% in smaller structures. An additional I(V) fine structure is observed in the 0.1 μm device, consistent with lateral quantization due to nonuniform strain.

Analysis of a fence-free platinum etch process

Abstract In a previous study we describe a high flow, Cl2-rich dry etch (DE) process which yields fence-free Pt etch structures. In that work we identify the existence of a transient fence defect, and show that it can cause the formation of an extremely shallow sidewall in the fully etched structure. We now expand upon this effort by documenting how several of the key DE parameters individually influence the sidewall profile. Through a series of four experiments, we found that: (a) the inclusion of Ar into the Cl2/CF4 gas mix promotes the formation of fencing; (b) insufficient total gas flow induces DE cone formation localized to the sidewalls of the etched Pt electrodes; (c) the inclusion of CF4 in the gas mix is unnecessary; and (d) the choice of self-bias voltage influences the critical dimension control and sidewall angle of the etched Pt electrodes.

Numerical Simulation of Etching and Deposition Processes

Accurate numerical simulation of microscopic surface topography evolution can facilitate the development of various etching and deposition processes for microelectronics applications. We have used numerical simulator SHADE, which is based on the shock-tracking method for surface evolution, to simulate processes that involve simultaneous etching and deposition. Examples are taken from two applications: conformal metal liner formation by the ionized magnetron sputter deposition process and Pt etching by ion beam and reactive ion etching processes. The numerical methods used for simulation and comparison between the simulation results and experimental observations are presented.

Fabrication of three‐terminal resonant tunneling devices in silicon‐based material

Laterally gated three‐terminal resonant tunneling devices have been fabricated from Si/Si1−xGex double‐barrier structures grown by atmospheric pressure chemical vapor deposition. The gate is insulated from the submicrometer vertical channel by a low‐temperature oxide and the entire fabrication scheme is compatible with current silicon technology. At T=77 K the resonant peak current can be modulated by 25% by applying a moderate gate voltage; at T=4.2 K, current modulation reaches 50%. We present calculations demonstrating that devices fabricated from optimized Si/Si1−xGex structures will pinch off fully at moderate gate voltages and operate at liquid nitrogen temperatures.

Dry etching of (Ba, Sr)TiO3 with Cl2, SF6, and CF4

Abstract The dry etch behavior of MOCVD (Ba, Sr)TiO3 (BST) films has been investigated with Cl2/SF6 and Cl2/CF4 gas mixtures. The etch response of blanket films was evaluated as a function of gas mix, self-bias voltage, and chamber pressure. Plasma deposition effects interfered with pristine etching by the Cl2/CF4 gas mixes. Etch rates for the Cl2/SF6 gas mixes exhibited a weak maxima at 10% SF6, which then dropped to a local minima at 20% SF6. The strongest etch response occurred with respect to self-bias voltage, where the etch rate exhibited a dependence that was approximately linear. Finally, at low rf powers the etch rate decreased monotonically with increasing pressure. However, at high power a weak maxima appeared at 20 mT. Overall, these power and pressure responses are consistent with physical sputtering. Therefore, it should be expected that the etch effluent of BST films will form sidewall redeposits on steeply sloped patterned structures in high dielectric constant capacitor DRAM memory applic...