Kejiu Zhang

New Insights on Dynamic Voltage Scaling of Multiphase Synchronous Buck Converter: A Comprehensive Design Consideration

This paper comprehensively investigates the power-related issues and introduces new control schemes in dynamic voltage scaling (DVS), which is now used in modern multi-core processor and multiprocessor system-on-chip to reduce operational voltage under light load conditions. With the aggressive motivation to boost dynamic power efficiency, the design specification of voltage transition (dv/dt) for the DVS is pushing the physical limitation of the multiphase converter design and the component stress. In this paper, the operation modes and modes transition during dynamic voltage transition are illustrated. Critical dead-times of driver IC design and system dynamics are first studied and then optimized. The excessive stress on the control MOSFET which increases the reliability concern is captured in boost mode operation. Feasible solutions are also proposed and verified by both simulation and experimental results. CdV/dt compensation for removing the adaptive voltage positioning effect and a novel nonlinear control scheme for smooth transition are proposed for dealing with fast-voltage positioning. Optimum phase number control during dynamic voltage transition is also proposed and triggered by voltage identification delta to further reduce the dynamic loss. For experimental verification, a 200 W, six-phase synchronous buck converter is implemented with the proposed schemes.

Modeling and design optimization of planar power transformer for aerospace application

A new low profile, light weight, high power density and high efficiency planar transformer for aerospace application is presented. In this paper, a systematic optimizing procedure is illustrated with a detailed design of a flyback transformer. We use Double 2D Finite Element Method (FEM) [1] modeling strategies to calculate the power loss and to optimize the design. The strategies, interleaving and horizontal and vertical parallel windings for reducing the winding loss are discussed. A 6-layer PCB layout is shown to validate the design.

Design and analysis of three-port DC/DC converters for satellite platform power system

Mass is one of the most important design constraints for the satellite power system. In order to achieve maximal solar power harvesting, battery charge/discharge control, and bus voltage regulation, normally several independent converters will be required, resulting in a heavy and bulky power system. This paper proposes a compact and efficient solution by using integrated three-port converter to achieve all above-mentioned functions within one single converter, therefore much lighter and smaller than the conventional system. The three-port topology is obtained by simply adding a switch and a diode to the conventional half-bridge converter. Moreover, zero-voltage switching is realized for all switches to reduce switching loss. The topology and circuit design is discussed in detail. In addition, the system construction is introduced, which adopts a distributed structure to obtain redundancy and maximize solar power harvesting for each individual PV panel. The proposed design is verified by experimental results.

Analysis and design of distributed transformers for solar power conversion

In this paper, a high efficiency, low profile design of distributed transformers (DT) for grid-tied photovoltaic (PV) inverter is presented. The proposed DTs fully integrated into the dual-flyback converter maximize the DC/DC stage efficiency in whole load conditions. The developed DTs with the built-in current sensing transformer allows the converter works in boundary conduction mode (BCM) or discontinues conduction mode (DCM) due to the variable nature of solar power with zero current switching (ZCS). Analytical loss model is established to optimize the value of magnetizing inductance which determines the switching frequency and converter overall efficiency. Various techniques are also taken to minimize the winding loss of the DTs. The experimental prototype employing the DTs achieves over 96% efficiency at full load condition.

Analysis and design of dynamic voltage regulation in multiphase buck converter

Dynamic voltage regulation (DVR) [1] is now widely used in microprocessors and system on chip (SOC) systems to reduce operational voltage under light load condition. With the aggressive motivation to reduce power consumption, the design specification of voltage transition (dv/dt) for the DVR is pushing the limit of the multiphase converter design and the component stress as well. In this paper, a novel control scheme is proposed for dealing with fast voltage positioning, i.e. upward and downward. The scenario of reverse current flowing is carefully studied based on the MOSFET parasitic model and experiment results. The stress on the HS MOSFET is also addressed. The effectiveness of the proposed scheme is verified by both simulation and experiment result.

Low voltage flyback DC-DC converter for power supply applications

In this paper, we design a low voltage DC-DC converter with a flyback transformer. The converter will be used as a biased power supply to drive IGBTs. The flyback transformer using planar EI-core is designed and simulated using ANSYS PExprt software. Besides, anLT3574 IC chip from Linear Technology has been chosen for converter control. Finally, the converter modeling and simulation are presented and PCB layout is designed.

Novel digital control schemes of dynamic current sharing for multiphase buck converter

High frequency load transient response and dynamic voltage scaling are two most important performance metrics in multiphase voltage regulator design to support high current dynamic loads, such as processor. As load frequency is increased up to MHz range or the regulator is enforced to run in boost operation mode during dynamic voltage downward transition, the voltage regulator suffers from imbalanced phase current which can introduce extra power loss and electrical stress on power components thus degrade the reliability of the overall system. In this paper, positive current sharing during high frequency load transient and negative current sharing during dynamic voltage downward transition are thoroughly studied. Load frequency detection scheme for disabling the nonlinear PWM control loop in high frequency transient is presented, and protection in the loop is proposed to accurate cycle by cycle current limiting scheme to crank the maximum current and mitigate the beat frequency oscillation are proposed. Critical design parameters in MOSFET driver IC design and adaptive voltage positioning (AVP) loop bandwidth are optimized. Dynamic power loss is reduced due to suppressed circulating current among phases. Experiment results are provided as verification of the analyses and solutions.

New insights on multiphase synchronous buck converter design: A comprehensive consideration

This paper comprehensively discusses the multiphase power converter design and introduces new control schemes in dynamic operations, which are now used to supply the power for modern Multi-Core processor (MCP) and multiprocessor System-on-Chip (MPSoC). With the aggressive motivation to boost dynamic power efficiency, the design specification of the VR is pushing the physical limitation of the multiphase converter design and the component stress as well. In this paper, the operation modes and PWM drive interface to achieve phase shedding are first illustrated. Robust driver operation is ensured when exiting the tri-state for long time. Nonlinear control scheme is introduce to minimize the voltage excursion during load transient. CdV/dt compensation for removing the AVP effect and novel nonlinear control scheme for smooth transition are proposed for dealing with fast voltage positioning. For experimental verification, a 400 W six phase synchronous buck converter is implemented with the proposed schemes.