Kelvin D. Goveas

Floating point processing unit with forced arithmetic results

Reservation station for a floating point processing unit

Using a shuffle unit to implement shift operations in a processor

Reservation station including addressable constant store for a floating point processing unit

Processor that predicts floating point instruction latency based on predicted precision

Method for floating point round to integer operation

Processor with reconfigurable floating point unit

PROCESSOR AND METHOD IMPLEMENTED BY A PROCESSOR TO IMPLEMENT MASK LOAD AND STORE INSTRUCTIONS

Processor with power saving reconfigurable floating point unit decoding an instruction to single full bit operation or multiple reduced bit operations

FLOATING POINT MULTIPLY-ADD UNIT WITH DENORMAL NUMBER SUPPORT