Kelvin Qiu

Design and modeling for chip-to-chip communication at 20 Gbps

This paper presents the design of serial chip-to-chip communication at 20 Gbps including modeling and correlation for PCBs (Printed Circuit Boards) with FR4 substrate materials. The entire channel under investigation includes two packages, a 21-layer ceramic and a 12-layer organic, and a 22-layer PCB. A probing station, microprobes and a VNA are used to measure the entire channel S-parameters and the measurement is correlated to the simulation up to 20 GHz. Extended study for the channel with low loss PCB substrate material is simulated. Time-domain eye comparisons for the FR4 channel, low loss channel, and the FR4 channel with equalization are given. A general design rule as well as new technologies for the high-speed channel design at 20 Gbps and beyond are discussed and given in the conclusion.

ASIC package design optimization for 10 Gbps and above backplane serdes links

This paper discussed the package selection and BGA signal pin assignment consideration for high-end ASIC design with over 400 SerDes (Serializer Deserializer) pairs for >;10Gbps backplane interface. The ASIC package is using advanced high-performance organic build-up (BU) materials like GX13, GZ41 and thinner core in the stack-up to help reduce the package loss and improve the signal transmission on the highspeed SerDes links. For return loss and insertion loss studies, the main objectives are to investigate the core thickness, BU material properties, and routing configurations impact on the differential signalling. The design suggestions are then made at each area for performance and cost optimization. For crosstalk studies, various pin-out patterns for transmit to transmit or receive to receive signals, and transmit to receive signals, have been designed and studied to investigate signal coupling and PCB escape routing requirements. Both frequency and time domain simulations are performed to compare the signal isolation performance. The most optimized pin-out is then selected to achieve the overall required system performance. Lastly, various package substrate samples with different BU materials, core thicknesses and crosstalk structures are manufactured to validate package design performance using probe station technique.

Characterization of PCB dielectric properties using two striplines on the same board

Signal integrity (SI) and power integrity (PI) modelling and design require accurate knowledge of dielectric properties of printed circuit board (PCB) laminate dielectrics. Dielectric properties of a laminate dielectric can be obtained from a set of the measured S-parameters on a PCB stripline with a specially designed through-reflect-line (TRL) calibration pattern. In this work, it is proposed to extract dielectric properties from the measurements of S-parameters on the two 50-Ohm stripline structures of the same length, but different widths of the trace, designed on the same layer of a PCB. The dielectric properties on these two lines should be identical. However, an application of the simplest “root-omega” technique to extract dielectric properties of the substrate would lead to the ambiguity in the extracted data. This is because the conductor surface roughness affects the measured S-parameters and is lumped in the extracted dielectric data. This problem of ambiguity in the dielectric properties extraction can be overcome using the approach analogous to the recently proposed method to separate dielectric and conductor losses on PCB lines with different widths and roughness profiles [1].

PCB via to trace return loss optimization for >25Gbps serial links

High speed serial links usually have extremely tight requirement on the quality of the signal channels, in terms of insertion loss and return loss. Along with an end-to-end channel design, the transition from plated-through-hole (PTH) via to fan-out traces on printed circuit board (PCB) creates unavoidable impedance discontinuity, which greatly impacts the channel return loss performance. It is important to understand and model this discontinuity for optimization purpose. This paper discusses several approaches of improving the channels properties, by optimizing the via-to-trace transition. Considering the impedance continuity at via to trace fan-out region, usually bigger anti-pad size (to reduce capacitive discontinuity) and larger return-path area (to reduce inductive discontinuity) are employed. In this paper, we inserted a short segment of fan-out-traces, named as “transition traces”, with slightly lower impedance than the system impedance; it significantly helps on improving the overall return loss performance, while being able to take care of the above-mentioned capacitive and inductive discontinuities very well. Besides, the impact of various parameters, including transition trace impedance, anti-pad sizes on different layers, is analyzed; and the optimum combination of these design parameters is suggested. Lastly, the manufactured test board is measured to verify the optimization method.

ASIC package to board BGA discontinuity characterization in >10Gbps SerDes links

High performance ASIC packages are typically mounted on the PCB using BGA solder ball technology; ASIC package to board BGA transition creates impedance discontinuity in the multi-gigabit signaling channel. It is important to understand and model this discontinuity accurately to improve end to end channel design in system level. Usually when the channel is simulated, instead of modeling the package with the PCB together in one model, also known as one piece model, separate models are built for package and PCB and the individual models are then cascaded using the circuit simulator. If the models are not setup correctly in the field solvers, i.e. port definition, it may not capture the transition behavior correctly and hence makes the cascaded channel model results differ from one piece model and/or real channel measurement. This paper discusses the detailed modeling of the BGA solder ball transition to enable the model concatenation method suitable to be used for system level channel prediction. The package only model, board only model and one piece model were simulated upto 20GHz using either lump port or wave port setup in ANSYS HFSS field solver. The cascaded model with wave port connection and one piece model are found well matched. The lump-port connection can introduce extra parasitic inductance at the BGA connection point and hence is not recommended. Hardware (package and PCB test samples) have been built to characterize this transition behavior for model to hardware correlation. The FSA (Feature Selected Validation) method is used to quantify the correlation results, both insertion loss and return loss are compared to gain confidence on the simulation results and high-speed channel prediction.

Enabling terabit per second switch linecard design through chip/package/PCB co-design

Widespread use of the Web 2.0 Internet applications such as video streaming and social networking are continuously demanding higher bandwidth network equipment. Electrical designers increasingly face more and more challenges to deliver higher speed products within short development cycle due to design complexity and new multi-GHz signal integrity problems. This paper presents a modeling and simulation methodology through chip/package/PCB (printed circuit board) co-design and co-optimization to enable a terabit per second network switch linecard design. Channel design techniques such as BGA (Ball Grid Array) pin backdrill, via tuning, and low loss interconnects are outlined. Full wave 3D modeling techniques with optimal model segmentation, model cascading and model optimization are discussed. At the end, correlation between lab measurement and simulation in both frequency and time domains are investigated.

Design of package BGA pin-out for >25Gb/s high speed SerDes considering PCB via crosstalk

Fast growing bandwidth demands for networking and data center applications continuously face difficult signal integrity challenges. Among them, serializer/deserializer (SerDes) package pin-out and its corresponding printed circuit board (PCB) via crosstalk have become a significant source of high jitter and limit the performance of high speed serial links. In this paper, a variety of far-end crosstalk (FEXT) and near-end crosstalk (NEXT) SerDes pin-out patterns are designed and investigated to explore the crosstalk performance for interfaces running 25Gb/s and beyond. The impact of PCB routing layer selection and via stub are also considered. Both frequency domain and time domain analysis are studied based on 3-dimensional (3D) full wave electromagnetic (EM) simulation, and the results are compared along with the calculated integrated crosstalk noise (ICN) to find the pattern with better signal isolation. A PCB test vehicle is designed and manufactured to provide measurement and verification results by using broadband micro-probes and multi-port vector network analyzer (VNA). The optimized pin-out is then selected to evaluate the overall link performance based on the input/output buffer information specification algorithmic modeling interface (IBIS-AMI) model from silicon vendors.

Ferrite bead model extraction and its application in high-performance ASIC analog power filtering

High performance ASICs (Application-Specific Integrated Circuits) are getting dominant in modern high-end networking systems. Provisions on the power supplies for these extremely high integrated ASICs are somewhat demanding and strict especially for sensitive analog power rails. To meet the power requirements from ASIC vendors, ferrite bead is used to fulfil the analog filtering. In order to complete the filter design and analysis, a genetic algorithm is developed to extract circuit model from a ferrite bead impedance curve. The extracted circuit model is used for filter performance analysis. As a case study, the designed filter is implemented on a PCB (printed circuit board) in a real product. Measured power noise on the analog power rail confirms that the ferrite bead filter design is successful and the analog power meets the specifications from ASIC vendors.

Analytical equivalent circuit modeling for multiple core vias in a high-speed package

Core vias found in the packages of high-speed ICs can have a large impact on overall channel performance. Thus accurately modeling core vias in the package is essential. In this paper analytical methodologies are used to calculate equivalent circuit models of core vias.

Signal transition structure optimization for 16 Gbps SFP cage and PCB interface

SFP (Small Form-factor Pluggable) module and SFP cage form an interface between a network device and an optic cable or a copper cable for data communication and telecommunication. Data rate on such an interface for a high-speed channel varies from 1 Gbps (Gigabit per second) to 10 Gbps for the existing products, and products with the data rate of 16 Gbps are under development. Due to the differences of networking platform, data rate, and channel length, this interface can be directly driven by an ASIC (Application-Specific Integrated Circuit) or an EDC (Electric Dispersion Compensation) chip in electric domain. Compliance tests are enforced on the interface to fulfil the interoperability requirement, which makes the signal integrity work extremely challenge at 16 Gbps. Since the discontinuity on the interface of a PCB (Printed Circuit Board) and a SFP cage is dominant in the electric path, optimization such an interface structure is critical to meet the compliance specification and achieve system BER (Bit Error Rate). In this paper, a fast via tool is used initially for quick solution about the interface structure optimization. The optimized parameter is verified in a full-wave modelling, and the via structure related resonance is observed and identified. Based on the given SFP cage footprint and observed resonance, a new signal transition structure for the SFP cage and PCB interface is finally proposed, modelled and optimized.