Bichen Chen

Characterization of PCB dielectric properties using two striplines on the same board

Signal integrity (SI) and power integrity (PI) modelling and design require accurate knowledge of dielectric properties of printed circuit board (PCB) laminate dielectrics. Dielectric properties of a laminate dielectric can be obtained from a set of the measured S-parameters on a PCB stripline with a specially designed through-reflect-line (TRL) calibration pattern. In this work, it is proposed to extract dielectric properties from the measurements of S-parameters on the two 50-Ohm stripline structures of the same length, but different widths of the trace, designed on the same layer of a PCB. The dielectric properties on these two lines should be identical. However, an application of the simplest “root-omega” technique to extract dielectric properties of the substrate would lead to the ambiguity in the extracted data. This is because the conductor surface roughness affects the measured S-parameters and is lumped in the extracted dielectric data. This problem of ambiguity in the dielectric properties extraction can be overcome using the approach analogous to the recently proposed method to separate dielectric and conductor losses on PCB lines with different widths and roughness profiles [1].

Analytical and numerical sensitivity analyses of fixtures de-embedding

De-embedding procedures are sensitive to manufacturing variations in test fixtures, as well as inaccuracies associated with the calibration and measurement process. Such sensitivities can propagate through de-embedding procedures, resulting in amplified errors. In this paper, analytical and numerical techniques are used to perform sensitivity studies on both simulation and measurement data, with respect to de-embedding.

Validating the transmission-line based material property extraction procedure including surface roughness for multilayer PCBs using simulations

Accurate frequency-dependent dielectric properties are important for accurate modeling of signal and power integrity problems. One method for extracting dielectric properties from fabricated multilayer printed circuit boards is based on the measured electrical property of fabricated transmission lines, denoted the “Root-omega” method. In this paper, the “Root-omega” method applied to the cases with smooth and rough conductors is validated using simulations. Potential errors in the procedure are discussed.

Differential integrated crosstalk noise (ICN) reduction among multiple differential BGA and Via pairs by using design of experiments (DoE) method

The integrated crosstalk noise (ICN) has been wildly used as an alternative to the insertion crosstalk ratio (ICR) for channel crosstalk evaluation in the IEEE 802.3ba standard. In this work, a differential ICN analysis is performed for several configurations of package-to-PCB transitions. Using the design of experiment (DoE) statistical method, differential ICN is quickly estimated for various input factors such as pin mapping, physical dimensions, and level of shielding. Optimization guide line is proposed to maintain the tradeoff among the differential ICN, design space, and manufacturing cost.

Improved “Root-Omega” Method for Transmission-Line-Based Material Property Extraction for Multilayer PCBs

Electrical properties of dielectric substrate are critical in designing high-speed products in terms of signal and power integrity. It is important to accurately characterize the dielectric properties to avoid overestimating or underestimating in the design. This paper proposes the improved “Root-Omega” method for extracting dielectric properties from fabricated multilayer printed circuit boards. Based on the electrical properties of fabricated transmission lines, the improved “Root-Omega” method applied to cases with smooth and rough conductors is validated using simulations. Error sensitivity analysis is performed to demonstrate the potential errors in the original “Root-Omega” procedure and the error sensitivity is significantly reduced by the proposed improvements.

Effectiveness analysis of de-embedding method for typical TSV pairs in a silicon interposer

In this paper, a de-embedding method to extract the performance of a Through-Silicon-Via (TSV) pair is proposed, using a set of specially designed test patterns to remove the pads and connection trace. Considering in real implementations, wafer probe measurements are required to access the test structures, and any errors in the probe calibration affect the test pattern measurements, a micro-probe model is built in with the test. Short-Open-Load (SOL) calibration method is used with the simulation results to calibrate or correct to the tips of the micro-probe used in all test patterns. Calibrated responses for the test patterns consisting of probing pads, traces and TSV pair, thus are used with previously proposed de-embedding algorithm to characterize the TSV pair. The effectiveness and the robustness of the de-embedding method against probe calibration errors are tested with the full wave simulation results and analytical calculations.

Error bounds analysis of de-embedded results in 2x thru de-embedding methods

In this paper, an error bound analysis is performed for 2x thru de-embedding methods: AFR (Automatic Fixture Removal) and SFD (Smart Fixture De-embedding). Basically, a certain amount of error is assumed to exist in S11 of 1x. This error will cause the de-embedded results to vary within a certain range. The upper bound and lower bound of the magnitude of the de-embedded results are given.

Thru-Reflect-Line Calibration Technique: Error Analysis for Characteristic Impedance Variations in the Line Standards

In this paper, we analyze the impact of characteristic impedance variations among standards on the accuracy of the thru-reflect-line (TRL) calibration technique. The impedance transformer method is adopted to derive the expressions of the calibration coefficient errors due to the manufacturing tolerances. It is found that three factors can affect the magnitude of the errors in the calibration coefficients (c/a and b terms), which are crucial to get the final calibrated results. The first factor is related to the original parameters of the error networks (test fixtures): the larger the insertion losses, the smaller the error in b; the error in c/a may see an opposite trend if the error network is lossy instead of lossless. The second factor is denoted as the phase contribution (one of the three multipliers of the derived error expression): the magnitude of this error contributing item is approximately equal to the ratio of two hyperbolic sine functions, the variables of which are the length of Line and the length difference between Line and Thru, respectively. The third factor comes from the impedance differences between Thru and Line: the smaller the impedance variation, the smaller the error. The error analysis, presented here, can help engineers evaluate the calibration accuracy by analyzing the error contributing items. It also can be further used to guide test fixture designs to maximize TRLs error immunity to the transmission line characteristic impedance variations.