Kenichi Ohhata

Quantum Encryption Communication Over a 192-km 2.5-Gbit/s Line With Optical Transceivers Employing Yuen-2000 Protocol Based on Intensity Modulation

A Y-00 transceiver for quantum encryption communication systems employing the Yuen-2000 protocol based on optical intensity modulation, which utilizes the quantum effect of coherent light has been developed and tested in field experiments. These experiments involved repeated transmission over a 192-km line on an existing commercial optical communication network with a bit-rate of 2.5 Gb/s based on STM-16 or OC-48. In addition, the affinity of the developed system for existing networks and communication protocols (Gigabit Ethernet and Fibre Channel) was examined. Subsequently, three optical fiber amplifiers were inserted as intermediate repeaters to give a non-repeated transmission distance of 48 km. The bit error rate after 192-km transmission was 10-12 with an optical power of -19.4 dBm at the receiving end. In addition, it was confirmed that if an eavesdropper increased the received optical power, the bit error rate converged to about 5 × 10- 1 and the identification of the true signal levels was virtually impracticable. These experimental results confirmed the high affinity between the Y-00 system and existing optical commercial networks and protocols used in the fundamental experiments. It was also apparent that the realization of highly secure optical communication networks was feasible. The performance of the Y-00 transceiver can be expected to improve to meet the strictest security evaluation.

Design of a 770-MHz, 70-mW, 8-bit Subranging ADC Using Reference Voltage Precharging Architecture

This paper describes a high-speed, low-power CMOS subranging analog-to-digital converter (ADC). A reference voltage precharging architecture and the introduction of a comparator with a built-in threshold voltage in the fine ADC are proposed to reduce the settling time of the reference voltage. A T/H circuit with a body-bias control circuit is employed to reduce distortion at a high sampling rate. Moreover, a V TH generator using a replica of the original comparator is also proposed to compensate for V TH deviation due to the process variations. A test chip was fabricated using 90-nm CMOS technology, and showed a high-sampling rate of 770 MS/s and a low-power consumption of 70 mW.

Design of a 4

This paper describes the design and experimental results of a 4 × 10 Gb/s vertical-cavity surface-emitting laser (VCSEL) driver using the asymmetric emphasis technique. Conventional symmetric emphasis techniques can compensate for the influences of parasitic capacitances; however, they cannot compensate for the nonlinear effects of a VCSEL. To overcome this problem, an asymmetric emphasis technique that can separately control the emphasis pulses at the rising and falling edges is proposed. This allows fast transition in VCSEL output waveform suppressing ringing. A driver circuit that has two separate emphasis circuits for the rising and falling edges is proposed in order to implement the asymmetric emphasis technique. This configuration enables us to separately control the height, width, and setup time of the emphasis pulses at the rising and falling edges. The test chip fabricated by using 90-nm CMOS technology generates a clearly open optical eye at a data rate of 10 Gb/s, and we can confirm the existence of a wide phase margin by a transmission experiment.

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A 25 Gb/s laser diode (LD) driver has been developed on the basis of standard 65 nm CMOS technology for optical interconnects. The LD driver consists of a main driver capable of providing an average current of 30 mA and a predriver providing a gain of 20 dB. The main driver uses mutually coupled inductors to adjust the inductive peaking to improve eye patterns under various packaging conditions. The predriver uses CMOS active feedback to achieve a wide bandwidth and high gain, despite its small size and low power consumption. The fabricated circuit achieves data rates of 25 Gb/s, consumes 156 mW (6.3 mW/Gb/s) and occupies an area of 0.011 mm2 .

10 Gb/s VCSEL Driver Using Asymmetric Emphasis Technique in 90-nm CMOS for Optical Interconnection

This paper describes the design and experimental results of a 17 Gb/s vertical-cavity surface-emitting laser (VCSEL) driver using a double-pulse asymmetric emphasis technique. In this technique, the first pulse compensates for the parasitic capacitances and the second pulse compensates for the ringing, which enables a good eye opening even when the data rate increases. A test chip fabricated using a 90-nm CMOS technology generates a clearly open optical eye at a data rate of 17 Gb/s, which is approximately twice the VCSEL bandwidth.

A 25 Gb/s 65-nm CMOS Low-Power Laser Diode Driver With Mutually Coupled Peaking Inductors for Optical Interconnects

This paper describes a 25Gb/s laser diode (LD) driver based on a standard 65nm CMOS technology for optical interconnects. The LD driver consists of a main driver capable of providing an average current of 30mA and a pre-driver that provides a gain of 20dB. The main driver uses mutually coupled inductors to adjust peaking for various packaging conditions. The pre-driver uses CMOS active feedback to achieve wide bandwidth and high gain, despite compact dimensions and low power consumption. The fabricated circuit achieves 25Gb/s data rates while consuming 142mW (5.2mW/Gb/s) and occupying an area of 0.011mm2.

17 Gb/s VCSEL driver using double-pulse asymmetric emphasis technique in 90-nm CMOS for optical interconnection

A 10-Gb/s optical transceiver using the Yuen 2000 (Y-00) encryption protocol was developed. The key device in the transceiver, a 10-GS/s, 10-bit digital-to-analog converter (DAC) LSI, was fabricated using 0.25-μm SiGe BiCMOS technology. Circuit techniques such as segmented architecture, parasitic capacitance separation using the base-common transistor, and the usage of a common mode logic (CML) driver were employed to minimize glitches. The Y-00 transceiver equipped with the DAC LSI operated at 10 Gb/s. Moreover, a 300-km transmission experiment performed at a data rate of 10 Gb/s proved that the developed transceiver can be used in a practical application when forward error correction is applied.

A 25Gb/s laser diode driver with mutually coupled peaking inductors for optical interconnects

This paper describes a high-speed low-power CMOS subranging analog-to-digital converter (ADC). A reference voltage precharging architecture and the introduction of a comparator with built-in threshold voltage in the fine ADC are proposed to reduce the settling time of the reference voltage. A T/H circuit with body-bias control circuit is employed to reduce the distortion at high sampling rate. The test chip fabricated using 90-nm CMOS technology shows a high-sampling rate of 770 MS/s and a low-power consumption of 70 mW.

10-Gb/s Optical Transceiver Using the Yuen 2000 Encryption Protocol

A 1-GHz, 17.5-mW, 8-bit subranging ADC was fabricated using 65-nm CMOS technology. We adopt an analog centric approach differing from the digital foreground calibration to reduce power dissipation. An offset cancelling charge-steering amplifier and the capacitive averaging technique effectively reduce the offset, noise, and power dissipation. Moreover, the compensation circuit for the noise current from the comparator can also reduce the power dissipation. The test chip fabricated in 65-nm digital CMOS technology shows a high-sampling rate of 1 GHz and low-power dissipation of 17.5 mW. This chip achieved the FOM of 118 fJ/conv.-step.

A 770-MHz, 70-mW, 8-bit subranging ADC using reference voltage precharging architecture

This paper describes a high-speed CMOS track-and-hold (T/H) circuit with low distortion. We propose a T/H circuit with a body-bias control circuit to reduce distortion. This control circuit maintains a constant body bias for a switching MOS transistor in tracking mode. This reduces the variation in the threshold voltage due to the body-bias effect, thereby resulting in low distortion. The test chip fabricated using 90-nm CMOS technology shows a high SFDR of 56.3dB at a sampling frequency of 1GHz.