Kiichi Yamashita

Quantum Encryption Communication Over a 192-km 2.5-Gbit/s Line With Optical Transceivers Employing Yuen-2000 Protocol Based on Intensity Modulation

A Y-00 transceiver for quantum encryption communication systems employing the Yuen-2000 protocol based on optical intensity modulation, which utilizes the quantum effect of coherent light has been developed and tested in field experiments. These experiments involved repeated transmission over a 192-km line on an existing commercial optical communication network with a bit-rate of 2.5 Gb/s based on STM-16 or OC-48. In addition, the affinity of the developed system for existing networks and communication protocols (Gigabit Ethernet and Fibre Channel) was examined. Subsequently, three optical fiber amplifiers were inserted as intermediate repeaters to give a non-repeated transmission distance of 48 km. The bit error rate after 192-km transmission was 10-12 with an optical power of -19.4 dBm at the receiving end. In addition, it was confirmed that if an eavesdropper increased the received optical power, the bit error rate converged to about 5 × 10- 1 and the identification of the true signal levels was virtually impracticable. These experimental results confirmed the high affinity between the Y-00 system and existing optical commercial networks and protocols used in the fundamental experiments. It was also apparent that the realization of highly secure optical communication networks was feasible. The performance of the Y-00 transceiver can be expected to improve to meet the strictest security evaluation.

Design of a 770-MHz, 70-mW, 8-bit Subranging ADC Using Reference Voltage Precharging Architecture

This paper describes a high-speed, low-power CMOS subranging analog-to-digital converter (ADC). A reference voltage precharging architecture and the introduction of a comparator with a built-in threshold voltage in the fine ADC are proposed to reduce the settling time of the reference voltage. A T/H circuit with a body-bias control circuit is employed to reduce distortion at a high sampling rate. Moreover, a V TH generator using a replica of the original comparator is also proposed to compensate for V TH deviation due to the process variations. A test chip was fabricated using 90-nm CMOS technology, and showed a high-sampling rate of 770 MS/s and a low-power consumption of 70 mW.

Design of a 4

This paper describes the design and experimental results of a 4 × 10 Gb/s vertical-cavity surface-emitting laser (VCSEL) driver using the asymmetric emphasis technique. Conventional symmetric emphasis techniques can compensate for the influences of parasitic capacitances; however, they cannot compensate for the nonlinear effects of a VCSEL. To overcome this problem, an asymmetric emphasis technique that can separately control the emphasis pulses at the rising and falling edges is proposed. This allows fast transition in VCSEL output waveform suppressing ringing. A driver circuit that has two separate emphasis circuits for the rising and falling edges is proposed in order to implement the asymmetric emphasis technique. This configuration enables us to separately control the height, width, and setup time of the emphasis pulses at the rising and falling edges. The test chip fabricated by using 90-nm CMOS technology generates a clearly open optical eye at a data rate of 10 Gb/s, and we can confirm the existence of a wide phase margin by a transmission experiment.

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This paper describes the design and experimental results of a 17 Gb/s vertical-cavity surface-emitting laser (VCSEL) driver using a double-pulse asymmetric emphasis technique. In this technique, the first pulse compensates for the parasitic capacitances and the second pulse compensates for the ringing, which enables a good eye opening even when the data rate increases. A test chip fabricated using a 90-nm CMOS technology generates a clearly open optical eye at a data rate of 17 Gb/s, which is approximately twice the VCSEL bandwidth.

10 Gb/s VCSEL Driver Using Asymmetric Emphasis Technique in 90-nm CMOS for Optical Interconnection

A 10-Gb/s optical transceiver using the Yuen 2000 (Y-00) encryption protocol was developed. The key device in the transceiver, a 10-GS/s, 10-bit digital-to-analog converter (DAC) LSI, was fabricated using 0.25-μm SiGe BiCMOS technology. Circuit techniques such as segmented architecture, parasitic capacitance separation using the base-common transistor, and the usage of a common mode logic (CML) driver were employed to minimize glitches. The Y-00 transceiver equipped with the DAC LSI operated at 10 Gb/s. Moreover, a 300-km transmission experiment performed at a data rate of 10 Gb/s proved that the developed transceiver can be used in a practical application when forward error correction is applied.

17 Gb/s VCSEL driver using double-pulse asymmetric emphasis technique in 90-nm CMOS for optical interconnection

This paper describes a high-speed low-power CMOS subranging analog-to-digital converter (ADC). A reference voltage precharging architecture and the introduction of a comparator with built-in threshold voltage in the fine ADC are proposed to reduce the settling time of the reference voltage. A T/H circuit with body-bias control circuit is employed to reduce the distortion at high sampling rate. The test chip fabricated using 90-nm CMOS technology shows a high-sampling rate of 770 MS/s and a low-power consumption of 70 mW.

10-Gb/s Optical Transceiver Using the Yuen 2000 Encryption Protocol

This paper describes a high-speed CMOS track-and-hold (T/H) circuit with low distortion. We propose a T/H circuit with a body-bias control circuit to reduce distortion. This control circuit maintains a constant body bias for a switching MOS transistor in tracking mode. This reduces the variation in the threshold voltage due to the body-bias effect, thereby resulting in low distortion. The test chip fabricated using 90-nm CMOS technology shows a high SFDR of 56.3dB at a sampling frequency of 1GHz.

A 770-MHz, 70-mW, 8-bit subranging ADC using reference voltage precharging architecture

In this paper, a method for controlling the driving current is discussed and then an asymmetric emphasis technique that individually controls its waveform at the rising and falling edges is proposed. The circuit implementation for the asymmetric emphasis technique is discussed and experimental results for the fabricated test chip is provided.

A 1-GHz, 56.3-dB SFDR CMOS track-and-hold circuit with body-bias control circuit

A sandwich structure type RF-MEMS variable capacitor is proposed, that consists of a movable middle plate, and fixed top and bottom plates having different areas. Simulation results show that the proposed capacitor can operate at a control voltage of less than 3.2V; it achieves a tuning range of 4.8:1 (capacitance: 630-130fF) in the range of 0 to 3.2V and at a frequency of 7.5GHz.

A 90-nm CMOS 4 × 10 Gb/s VCSEL driver using asymmetric emphasis technique for optical interconnection

This paper describes a feedthrough reduction technique for a track-and-hold (T/H) circuit with a body-bias control circuit. We propose a T/H circuit with a feedthrough canceller. This circuit cancels a leaking signal to the output node through the parasitic capacitance by using an opposite-phase signal. The simulation results using 90-nm CMOS technology demonstrate a feedthrough of -89.4dB and SFDR of 66dB at a sampling frequency of 5GHz.