Kenichi Oki

Crystallization at initial stage of low‐temperature polycrystalline silicon growth using ZnS buffer layer with 〈111〉 preferred orientation

We developed a low‐temperature growth technique for polycrystalline silicon (poly‐Si). When Si is deposited on glass substrates at 450 °C, it crystallizes as thickness increases, but 10‐nm‐thick layers of Si are mainly amorphous. Use of a ZnS buffer layer with 〈111〉 preferred orientation facilities crystallization of Si during the initial growth stages. The preferred orientation of poly‐Si on glass substrates is 〈110〉, while that of poly‐Si on the ZnS buffer layer is 〈111〉. This is probably due to local epitaxial growth on polycrystalline ZnS grains with 〈111〉 preferred orientation. Raman spectroscopy showed that the ZnS buffer layer significantly improved the crystallinity of 25‐nm‐thick Si layers.

Threshold voltage shift of amorphous silicon thin‐film transistors by step doping

The threshold voltage (VT) shift of hydrogenated amorphous silicon thin‐film transistors (a‐Si:H TFTs) by boron doping has been investigated. In TFTs with a uniformly doped structure (SiN/B‐doped a‐Si:H), VT shifts to a positive voltage by boron doping, while the field‐effect mobility decreases markedly. By using a step‐doped structure (SiN/undoped a‐Si:H/B‐doped a‐Si:H), the degradation of the field‐effect mobility by boron doping becomes less than that of a uniformly doped TFT with the same VT shift, and a VT shift of 3.5 V was obtained without degradation of the field‐effect mobility.

Noncrossing TFT matrix with reduced dc level shift and crosstalk

— A noncrossing TFT matrix and drive scheme that eliminates dc level-shift differences among data and reduces crosstalk without a storage capacitor is proposed. To compensate for the dc level shift, an extra TFT is added to each pixel. By applying a compensation pulse to the TFT, the dc level-shift differences among data are reduced to less than 0.01 V. The compensating TFT also provides redundancy. The peak-to-peak data voltage amplitude is lowered by changing the reference voltage according to the LC cell voltage polarity. By using the lowered data voltage and the shielded reference bus structure, crosstalk is reduced sufficiently to allow for 64 gray levels.