Tatsuya Kakehi

High Performance Low Temperature Polycrystalline Silicon Thin Film Transistors on Non-alkaline Glass Produced Using Diode Pumped Solid State Continuous Wave Laser Lateral Crystallization

High performance low temperature polycrystalline silicon (poly-Si) thin film transistors (TFTs) with large grains were created using diode pumped solid state (DPSS) continuous wave (CW) laser lateral crystallization (CLC), employing fabrication processes at 450°C. Field-effect mobilities of 566 cm2/Vs for the n-channel and 200 cm2/Vs for the p-channel were obtained for a thick Si film (100–150 nm) on a 300×300 mm non-alkaline glass substrate. The high performance of the TFTs is attributed to the predominantly (100)-oriented very large grains. With a decreasing Si-film thickness, the grain size decreases, and the surface orientation of the grain changes from (100) to other orientations. These effects lead to reduced field-effect mobility with decreasing Si-film thickness, but it is easy to obtain a high field-effect mobility of over 300 cm2/Vs, even with a 50 nm thick Si film, without special processing techniques. A complementary metal oxide semiconductor (CMOS) ring oscillator was fabricated using a thin Si film 65 nm thick to demonstrate the high circuit performance of CLC poly-Si TFTs by applying the simplest CMOS process technology. A delay of 400 ps/stage at a gate length of 1.5 µm and a supply voltage of Vdd=5.0 (V) was produced on a large non-alkaline glass substrate utilizing a fabrication temperature of 450°C. This crystallization method will lead to the fabrication of high-performance and cheap Si-LSI circuits on large non-alkaline glass substrates.

POLYCRYSTALLINE SILICON FORMED BY ULTRAHIGH-VACUUM SPUTTERING SYSTEM

Using an ultrahigh‐vacuum (UHV) sputtering system, we could grow two new methods of polycrystalline silicon films. The one is as‐deposited polycrystalline silicon on glass at substrate temperatures under 500 °C. The other is solid‐phase‐crystallization by thermal annealing of as‐deposited amorphous silicon films in a UHV. As‐deposited polycrystalline silicon films were oriented to (220) and grain sizes were determined from half‐width of x‐ray diffraction to be about 40 nm. From the deposition temperature dependence of the x‐ray diffraction peak intensity, the activation energy of the crystalline growth was calculated to be about 0.6 eV. Hydrogen atoms in the sputtering gas lower the reproducibility of as‐deposited poly‐Si. Polycrystalline silicon films produced by thermal annealing of as‐deposited amorphous silicon films at 550 °C in UHV have a (111) orientation. Field‐effect mobilities of the as‐deposited polycrystalline silicon film and the polycrystalline silicon film by UHV thermal annealing were 5 an...

12.3: High Throughput CW-Laser Lateral Crystallization for Low-Temperature Poly-Si TFTs and Fabrication of 16 bit SRAMs and 270MHz Shift Registers

Throughput improvement and fabrications of 4×4 bit SRAMs and 270 MHz shift registers are described for the CW-Laser Lateral Crystallization (CLC) of amorphous-Si on glass substrate. For the pixel array, effective area-crystallization rate is improved to 48cm2/s for 171ppi and 68cm2/s for 119ppi by 16 sub-laser-beams and 2m/s scanning speed.

Effect of hydrogen ion shower doping in polycrystalline silicon thin‐film transistors

We investigated the effect of hydrogen ion shower doping on polycrystallinesilicon thin‐film transistors (p‐Si TFTs). Hydrogen atoms were introduced to the channel region of p‐Si TFTs by PH3/H2 ion shower doping of the source/drain contact. Hydrogen concentration in the channel region can be controlled by altering the gate metal thickness. Hydrogen atoms affect the TFT’s threshold voltage shifts until it becomes negative, in n‐type TFTs. The threshold voltage shift depends on the hydrogen content of the channel region in p‐Si TFTs. This is explained by the existence of Si− 3 trap states in the grain boundaries.

Noncrossing TFT matrix with reduced dc level shift and crosstalk

— A noncrossing TFT matrix and drive scheme that eliminates dc level-shift differences among data and reduces crosstalk without a storage capacitor is proposed. To compensate for the dc level shift, an extra TFT is added to each pixel. By applying a compensation pulse to the TFT, the dc level-shift differences among data are reduced to less than 0.01 V. The compensating TFT also provides redundancy. The peak-to-peak data voltage amplitude is lowered by changing the reference voltage according to the LC cell voltage polarity. By using the lowered data voltage and the shielded reference bus structure, crosstalk is reduced sufficiently to allow for 64 gray levels.