Kenichi Sano

Low Temperature Pre-Epi Treatment: Critical Parameters to Control Interface Contamination

Several device concepts have been further evaluated after the successful implementation of epitaxial Si, SiGe and/or Si:C layers. Most of the next device generations will put limitations on the thermal budget of the deposition processes without making concessions on the epitaxial layer quality. In this work we address the impact of ex-situ wet chemical cleans and in-situ pre-epi bake steps, which are required to obtain oxide free Si surfaces for epitaxial growth. The combination of defect measurements, Secondary Ion Mass Spectroscopy, photoluminescence, lifetime measurements, and electrical diode characterization gives a very complete overview of the performance of low-temperature pre-epi cleaning methods. Contamination at the epi/substrate interface cannot be avoided if the pre-epi bake temperature is too low. This interface contamination is traceable by the photoluminescence and lifetime measurements. It may affect device characteristics by enhanced leakage currents and eventually by yield issues due to SiGe layer relaxation or other defect generation. A comparison of state of the art 200 mm and 300 mm process equipment indicates that for the same thermal budgets the lowest contamination levels are obtained for the 300 mm equipments.

All Wet Photoresist Strip by Solvent Aerosol Spray

The introduction of metal gates and high-k dielectrics in FEOL and porous ULK dielectrics in BEOL presents severe issues [1] and leads to the requirement of new chemistries and processes. A major challenge in cleaning is the removal of photoresist (PR) in both FEOL and BEOL. In current semiconductor device fabrication flow, the photoresist strip process in FEOL is mostly achieved by applying a sequence of plasma ashing followed by a wet-clean step with sulfuric-peroxide mixture (SPM). But in general, ashing leads to strong oxidation or etching of silicon substrate. Hence, several approaches for ashless PR strip have been reported, such as hot SPM [2] and the combination of a pre-treatment using high velocity CO2 aerosol [3].

Aging phenomena in the removal of nano-particles from Si wafers

With the continuous shrinkage of critical sizes in semiconductor manufacturing, nano-particles smaller than 100-nm are becoming a potential threat to devices in chips. Storage of wafers contaminated during process steps often results in a decrease of particle removal efficiency in subsequent clean, a phenomenon referred to as aging. In this work, the influence of aging on the removal of silica and silicon nitride nano-particles from hydrophilic Si wafers was studied for different storage conditions. Trends observed for aging as a function of particle size and for different tools indicated that aging will become an issue for critical cleans where substrate etching must be kept very low and the physical component of the clean must be decreased to prevent damage to fine structures. Controlling the relative humidity during storage helped in lowering the effect of aging.

Damage Clustering and Damage-Size Distributions After Megasonic Cleaning

Physically-assisted-cleaning methods, e.g. megasonic cleaning, are evaluated by comparing particle removal efficiency (PRE) with added damage. [1] By identifying and classifying the added defects and linking them to the cleaning conditions, we expect to identify the weak spots in device structures and propose improved cleaning conditions. Weak spots could be related to material properties (e.g. line width roughness, poly-Si height variation, poly grain interfaces, etc). Aim of this work is to investigate if the defect distribution is supported by a random distribution of damage sites. Moreover we will study the impact of the megasonic cleaning settings on the damage size distribution.

Removal of Nano-Particles by Mixed-Fluid Jet: Evaluation of Cleaning Performance and Comparison with Megasonic

Cleaning of nano-particles is becoming a major challenge in semiconductor manufacturing as efficient particle removal must be achieved without substrate loss and without damage to fragile structures. In this work cleaning performance and structural damage by a mixed fluid-jet technique were evaluated and directly compared to the performance of several megasonic systems. The test vehicles were hydrophilic Si wafers contaminated with 78-nm SiO2 particles and 70-nm poly-gatestack line patterned wafers. The results showed a broader process window for particle removal without damaging for the mixed fluid-jet technique compared to the megasonic systems.

Single-Wafer Wet Chemical Oxide Formation for Pre-ALD High-k Deposition on 300 mm Wafer

The surface preparation was done in a Dainippon Screen (DNS) single-wafer spin cleaning tool, SU-3000. 300-mm Si wafers (p-type, <100> and <110> ,Cz) were used for tests. The surface preparation recipe consisted of a HF etch step followed by DIO3 for pre-high-k interface layer formation. Due to a quick oxidation by O3, it was very difficult to obtain a uniform thin oxide surface. The original concentration of 10 ppm DIO3 had to be diluted to 1 ppm in the system. Consequently, this 1ppm slower oxidation rate and an optimized scanning pattern resulted in a uniform thin oxide. The HfO2 films were grown by Atomic Layer Deposition (ALD) in the ASM Polygon at 300°C with HfCl4 and H2O precursors. A five-cycle recipe was used for HfO2 monolayer growth in order to focus only on the HfO2 deposited interface between a Si sub-thin oxide and a HfO2 layer. TEM pictures were taken on a Tecnai F30 operating at 300 kV. Ellipsometer measurements were peformed on a KLA-Tencor Aset F5. Since ellipsometric thickness values of HfO2 layers are less accurate for thin high-k layers, more accurate Hf volume measurements were obtained via direct TXRF using an Atomika 8300 (W-Lb) TXRF instrument. XPS was measured by Thermo Theta300 with Al K-alpha X-ray (1486.6 eV) and used to characterize thin oxide ellipsometric thickness. C-V curves were measured by Agilent 4284A precision LCR meter at 100 kHz. Solid State Phenomena Online: 2007-11-20 ISSN: 1662-9779, Vol. 134, pp 53-56 doi:10.4028/www.scientific.net/SSP.134.53

Minimizing Wafer Surface Charging for Single-Wafer Wet Cleaning for 10 nm and beyond

Wafer charging has become an issue since single-wafer wet clean has been introduced and multiple aspects could be potential root causes. In chemistry and DIW process factors, typical process parameters; flow rate and time were re-evaluated. As an alternative solution, dilute NH4OH could reduce the wafer surface charging. Hardware parts were also investigated and wafer holding chuck-pin material was revealed to become a risk of discharging failure at edge of wafer. Ionizer has been known to discharge wafer surface; however, it is not enough to remove pre-existing charge from post DIW rinsed wafer. Soft X-ray is challenged to remove pre-existing charge and obtained initial positive result.

Application of Single-Wafer Wet Cleaning Prior to Epitaxial SiGe Process

Strained silicon engineering was first used at the 90-nm node. Nowadays, a series of techniques has seen wide-spread use and many derivatives are available because of their ease of integration and cost-effective features [ , ]. As a main part of stressor technique, embedded SiGe-S/D technology is reported to improve the pMOSFET drive current [ , ].

Impact of Galvanic Corrosion on Metal Gate Stacks

High-k gate dielectrics (HK), such as HfO2 or HfSiON, are being considered as the gate dielectric option for the 45nm node and beyond. In order to alleviate the Fermi-level pinning issue and to enhance the CET (Capacitive Effective Thickness) by generating the depletion layer in poly-Silicon gate, metal gate electrodes with proper work functions (WF) have to be used on the high-k dielectrics.

Challenges of Single-Wafer Wet Cleaning for Low Temperature Pre-Epitaxial Treatment of SiGe

Epitaxial deposition of strained Si and SiGe to improve electron and hole mobility and Vt shift is becoming more and more part of the standard CMOS processing [1,2]. One of the most important restrictions imposed on advanced CMOS processing is that on thermal budget. For epitaxial growth processes this thermal budget is quite high. The main contribution comes however not from the growth itself, but from the in-situ H2 bake necessary to remove any oxide traces left prior to epi. Without any pre-epi etch, removal of the native oxide requires at least a bake for several minutes at 900 ̊C or higher. When combined with a wet clean which removes the native oxide and passivates the surface (usually H or Cl), this temperature can be reduced to the range of 850-750 ̊C, although this is always at the cost of a remaining C and O peak at the epi-substrate interface.