Kenichi Yoda

Design and component test of a tiny processor based on the SFQ technology

An eight-bit SFQ processor has been designed and some key components have been tested to confirm feasibility of the large-scale SFQ digital circuit. The designed processor is composed of a one-bit ALU, two eight-bit registers with local clock generators, an instruction register, a five-bit program counter, a state controller, and a 32-byte register file. A bit-serial architecture and a distributed local clock architecture, where each register has its own local clock generator, have been employed in order to increase the local clock frequency. The target clock frequency is 16 GHz and 10 GHz for the NEC 2.5 kA/cm/sup 2/ and Hypres 1 kA/cm/sup 2/ Nb processes. On the circuit design level, we have used a data-driven self-timed architecture and a binary decision diagram, which reduce the timing design difficulty in high frequency operation. The processor, which contains 7,300 Josephson junctions, has been designed by using a cell-based design methodology with the assistance of a top-down CAD environment. We have successfully tested some important circuit blocks, including a one-bit ALU, eight-bit registers, and a demultiplexer for register files.

Design and component test of a 1-bit RSFQ microprocessor

Abstract We have designed a 1-bit rapid single flux quantum microprocessor based on simple architecture. The target local clock frequency is 10 GHz. The microprocessor consists of a 1-bit ALU, two 8-bit resistors, a program counter and a state controller. In order to reduce the complexity of the system and increase the clock frequency, a width of the data bus is reduced to 1-bit and the distributed local clock architecture is employed. Though the instruction set comprises only six operations, it includes all the basic operation required in general purpose computing. The circuit design of the microprocessor has carried out by using a binary decision diagram and a cell-based design methodology with the aid of top-down CAD environment. One of the important components of the microprocessor, a 1-bit ALU, which contains 730 Josephson junctions, has been implemented using the 1 kA/cm 2 Nb process and its successful operation is confirmed at low speed.

Cell-based top-down design methodology for RSFQ digital circuits

We propose a cell-based top-down design methodology for rapid single flux quantum (RSFQ) digital circuits. Our design methodology employs a binary decision diagram (BDD), which is currently used for the design of CMOS pass-transistor logic circuits. The main features of the BDD RSFQ circuits are the limited primitive number, dual rail nature, non-clocking architecture, and small gate count. We have made a standard BDD RSFQ cell library and prepared a top-down design CAD environment, by which we can perform logic synthesis, logic simulation, circuit simulation and layout view extraction. In order to clarify problems expected in large-scale RSFQ circuits design, we have designed a small RSFQ microprocessor based on simple architecture using our top-down design methodology. We have estimated its system performance and compared it with that of the CMOS microprocessor with the same architecture. It was found that the RSFQ system is superior in terms of the operating speed though it requires extremely large chip area.

Cell based design methodology for BDD SFQ logic circuits: a high speed test and feasibility for large scale circuit applications

We have proposed a cell-based design methodology for SFQ logic circuits based on a binary decision diagram (BDD) and implemented a BDD SFQ standard cell library using a Hypres Nb process. In this design methodology, any logic function can be implemented by connecting binary switches. Since the circuits are dual rail logic and do not need a global clock, difficulty in the timing design is reduced considerably. In our cell-based design approach, the cell library is composed of only five kinds of basic cells, whose circuit parameters are optimized so as to remove the inter-cell interaction. At the layout level, the cells have the identical size so that circuits can be implemented by simply embedding the basic cells. In this study we have performed an on-chip high-speed test of the BDD SFQ logic circuits. The test system consists of two four-bit data-driven self-timed (DDST) shift registers with a ladder type clock generator. We have confirmed 12 GHz operations of the BDD SFQ logic circuit. We have also examined circuit size dependence of the DC bias margin of large BDD SFQ circuits.

Logic operation at 5 Gb/s of an output interface for single-flux-quantum systems

High-speed logic operation of an output interface circuit for a single-flux-quantum (SFQ) system was demonstrated at a data rate of 5 Gb/s. Using NECs 2.5-kA/cm/sup 2/ Nb junction process, we designed, fabricated, and tested the interface circuit consisting of a 2-b SFQ demultiplexer and two Josephson latching drivers. We verified the proper operation of the demultiplexer. The interface can convert 5-Gb/s SFQ-pulse data into two-channel 2.5-Gb/s return-to-zero data with an amplitude of approximately 6 mV.

Design and implementation of a high-speed bit-serial SFQ adder based on the binary decision diagram

We have designed a high-speed SFQ bit-serial carry-save adder based on the binary decision diagram (BDD). A simple bit-serial carry-save adder based on the BDD we first designed has a carry-feedback loop. Its input data frequency is limited by the propagation delay in the feedback loop. In our second adder design, we have replaced one BDD gate with a nondestructive binary switch, by which we can eliminate the carry-feedback loop. We have designed the high-speed BDD SFQ bit-serial adder using the NEC 2.5 kA cm−2 Nb standard process and the CONNECT cell library. The circuit simulation indicates that the maximum operating frequency is 38 GHz and the dc bias margin at 10 GHz is ±23%. We have confirmed its correct operation in the on-chip high-speed test. The maximum operating frequency was found to be 23.8 GHz.

Cell-based design methodology for BDD RSFQ logic circuits: tolerance of basic cells to circuit parameter variations

We have proposed a cell-based design approach based on a binary decision diagram (BDD) for the design of rapid single flux quantum (RSFQ) logic circuits. In this design approach, any logic function can be implemented by simply embedding the limited number of basic cells. We have constructed a BDD RSFQ cell library and prepared a top-down CAD environment. In this study, we investigated the tolerance of the BDD RSFQ basic cells to the circuit parameter variations. It was found that theoretical and measured dc bias margins of the basic cells agree well if we assume appropriate parameter variations due to the fabrication process. The dependence of the dc bias margin of the circuits on the circuit size was also examined, where we have implemented a 2-bit multiplexer, a 4-bit data-driven self-timed shift register and a 1-bit ALU. The low-speed test results reveal that dc bias margin of the circuits containing several hundreds of Josephson junctions is about ±15%, whereas theoretical dc bias margin is about ±33%. This paper was presented at the 8th International Superconductive Electronics Conference, Osaka, Japan, 19–22 June 2001.