F. Matsuzaki

A single-flux-quantum logic prototype microprocessor

The complete operation of a microprocessor prototype based on the single-flux-quantum (SFQ) logic is described. The 8b SFQ microprocessor, fabricated using niobium Josephson-junction technology, performs computation at a 15.2GHz clock rate with power consumption of 1.6mW. The /spl mu/P contains 5000 Josephson junctions and 1300 cells on a 5mm/sup 2/ IC.

Design and component test of a tiny processor based on the SFQ technology

An eight-bit SFQ processor has been designed and some key components have been tested to confirm feasibility of the large-scale SFQ digital circuit. The designed processor is composed of a one-bit ALU, two eight-bit registers with local clock generators, an instruction register, a five-bit program counter, a state controller, and a 32-byte register file. A bit-serial architecture and a distributed local clock architecture, where each register has its own local clock generator, have been employed in order to increase the local clock frequency. The target clock frequency is 16 GHz and 10 GHz for the NEC 2.5 kA/cm/sup 2/ and Hypres 1 kA/cm/sup 2/ Nb processes. On the circuit design level, we have used a data-driven self-timed architecture and a binary decision diagram, which reduce the timing design difficulty in high frequency operation. The processor, which contains 7,300 Josephson junctions, has been designed by using a cell-based design methodology with the assistance of a top-down CAD environment. We have successfully tested some important circuit blocks, including a one-bit ALU, eight-bit registers, and a demultiplexer for register files.

Design and implementation of circuit components of the SFQ microprocessor, CORE1

We have designed, implemented and tested several circuit components of a prototype of the SFQ microprocessor, CORE1. CORE1 is a synchronously clocked 8 bit microprocessor based on a bit-serial architecture. We have designed its circuit components using a cell-based design approach and an automated top-down CAD environment. We have successfully obtained correct operations of all circuit components, including an instruction register, a program counter and a controller.

A behavioral-level HDL description of SFQ logic circuits for quantitative performance analysis of large-scale SFQ digital systems

Recently many single flux quantum (SFQ) logic circuits containing several thousands of Josephson junctions have been designed successfully by using digital domain simulation based on the hard ware description language (HDL). In the present HDL-based design of SFQ circuits, a structure-level HDL description has been used, where circuits are made up of basic gate cells. However, in order to analyze large-scale SFQ digital systems, such as a microprocessor, more higher-level circuit abstraction is necessary to reduce the circuit simulation time. In this paper we have investigated the way to describe functionality of the large-scale SFQ digital circuits by a behavior-level HDL description. In this method, the functionality and the timing of the circuit block is defined directly by describing their behavior by the HDL. Using this method, we can dramatically reduce the simulation time of large-scale SFQ digital circuits.

Design and component test of a 1-bit RSFQ microprocessor

Abstract We have designed a 1-bit rapid single flux quantum microprocessor based on simple architecture. The target local clock frequency is 10 GHz. The microprocessor consists of a 1-bit ALU, two 8-bit resistors, a program counter and a state controller. In order to reduce the complexity of the system and increase the clock frequency, a width of the data bus is reduced to 1-bit and the distributed local clock architecture is employed. Though the instruction set comprises only six operations, it includes all the basic operation required in general purpose computing. The circuit design of the microprocessor has carried out by using a binary decision diagram and a cell-based design methodology with the aid of top-down CAD environment. One of the important components of the microprocessor, a 1-bit ALU, which contains 730 Josephson junctions, has been implemented using the 1 kA/cm 2 Nb process and its successful operation is confirmed at low speed.

Cell-based top-down design methodology for RSFQ digital circuits

We propose a cell-based top-down design methodology for rapid single flux quantum (RSFQ) digital circuits. Our design methodology employs a binary decision diagram (BDD), which is currently used for the design of CMOS pass-transistor logic circuits. The main features of the BDD RSFQ circuits are the limited primitive number, dual rail nature, non-clocking architecture, and small gate count. We have made a standard BDD RSFQ cell library and prepared a top-down design CAD environment, by which we can perform logic synthesis, logic simulation, circuit simulation and layout view extraction. In order to clarify problems expected in large-scale RSFQ circuits design, we have designed a small RSFQ microprocessor based on simple architecture using our top-down design methodology. We have estimated its system performance and compared it with that of the CMOS microprocessor with the same architecture. It was found that the RSFQ system is superior in terms of the operating speed though it requires extremely large chip area.

Prototypic design of the single-flux-quantum microprocessor, CORE1

We have designed a prototype of a microprocessor based on single-flux-quantum logic. The microprocessor called CORE1 has seven instructions and represents the simplest implementation of our CORE (complexity-reduced) architecture concept. Both instructions and data are 8-bit-wide, bit-serial, and their bit operations are performed with 16 GHz local clocks. The microprocessor is composed of a controller, a 5-bit program counter, an 8-bit instruction register, two 8-bit registers and a bit-serial ALU. We put together these components and some substitute shift registers for a memory into one microprocessor made up of 1301 cells, 4999 Josephson junctions. Using floor plans, both block-level and cell-level simulation techniques, we completed the timing design of all signal lines between the components. The designed CORE1 chip executes each instruction in six system clocks and we estimated its performance and power consumption at 167 million instructions per second and 1.6 mW, respectively.

Cell based design methodology for BDD SFQ logic circuits: a high speed test and feasibility for large scale circuit applications

We have proposed a cell-based design methodology for SFQ logic circuits based on a binary decision diagram (BDD) and implemented a BDD SFQ standard cell library using a Hypres Nb process. In this design methodology, any logic function can be implemented by connecting binary switches. Since the circuits are dual rail logic and do not need a global clock, difficulty in the timing design is reduced considerably. In our cell-based design approach, the cell library is composed of only five kinds of basic cells, whose circuit parameters are optimized so as to remove the inter-cell interaction. At the layout level, the cells have the identical size so that circuits can be implemented by simply embedding the basic cells. In this study we have performed an on-chip high-speed test of the BDD SFQ logic circuits. The test system consists of two four-bit data-driven self-timed (DDST) shift registers with a ladder type clock generator. We have confirmed 12 GHz operations of the BDD SFQ logic circuit. We have also examined circuit size dependence of the DC bias margin of large BDD SFQ circuits.

Cell-based design methodology for BDD RSFQ logic circuits: tolerance of basic cells to circuit parameter variations

We have proposed a cell-based design approach based on a binary decision diagram (BDD) for the design of rapid single flux quantum (RSFQ) logic circuits. In this design approach, any logic function can be implemented by simply embedding the limited number of basic cells. We have constructed a BDD RSFQ cell library and prepared a top-down CAD environment. In this study, we investigated the tolerance of the BDD RSFQ basic cells to the circuit parameter variations. It was found that theoretical and measured dc bias margins of the basic cells agree well if we assume appropriate parameter variations due to the fabrication process. The dependence of the dc bias margin of the circuits on the circuit size was also examined, where we have implemented a 2-bit multiplexer, a 4-bit data-driven self-timed shift register and a 1-bit ALU. The low-speed test results reveal that dc bias margin of the circuits containing several hundreds of Josephson junctions is about ±15%, whereas theoretical dc bias margin is about ±33%. This paper was presented at the 8th International Superconductive Electronics Conference, Osaka, Japan, 19–22 June 2001.