Kenichiro Suzuki

A silicon electrostatic ultrasonic transducer

An electric ultrasonic transducer is developed by using a silicon IC process. Design considerations are first presented to obtain high sensitivity and the desired frequency responses in air. The measured transmitter sensitivity is 19.1 dB (0 dB=1 mu bar/V) at a point 50 cm away from the devices, when the devices are operated at 150 kHz. The receiving sensitivity is 0.47 mV/Pa in the 10-130-kHz range, with bias voltages as low as 30 V. An electronic sector scanning operation is also achieved by time-sequentially driving seven elements arranged in a linear array on the same chip. The results should be helpful in the design of phased-array transducers integrated with electronic scanning circuits.<<ETX>>

MOS Integrated silicon pressure sensor

An MOS integrated silicon-diaphragm pressure sensor has been developed. It contains two piezoresistors in a half-bridge circuit, and a new simple signal-conditioning circuit with a single NMOS operational amplifier. The negative temperature coefficient of the pressure sensitivity at the half-bridge is compensated for by a positive coefficient of the variable-gain amplifier with a temperature-sensitive integrated feedback resistor. The sensor was fabricated using the standard IC process, except for the thin diaphragm formation using the N2H4. H2O anisotropic etchant. Tile silicon wafer was electrostatically adhered to the glass plate to minimize induced stress. The -1750 ppm/°C temperature coefficient of sensitivity at the half-bridge was compensated for to less than +190 ppm/°C at the amplifier output in the 0- 70°C range. A less than 20-mV thermal-output offset shift was also Obtained after 26-dB amplification in the same temperature range.

Nonlinear analysis of a CMOS integrated silicon pressure sensor

This paper reports theoretical and experimental results of analysis on the nonlinear characteristics of a CMOS integrated pressure sensor with a square silicon diaphragm. It is shown that nonlinearity is caused by both the large diaphragm deflection and the nonlinear piezoresistance of the resistors. The optimum layout for the piezoresistors to minimize their nonlinearity is also shown. The measured nonlinearity for the fabricated device agrees well quantitatively with the numerically analyzed nonlinearity.

Single crystal silicon micro-actuators

A novel process suitable for fabricating single-crystal silicon microactuators is described. The process utilizes boron-diffused silicon etch stop to define the silicon microstructure thickness and a dry etch process to form narrow and deep trenches, followed by a silicon-to-glass bonding step and subsequent unmasked wafer dissolution. For rotational microactuators, polysilicon trench filling and sacrificial layer patterning are added to define a rotor stopper. The process successfully provided linear (stepped and resonant) and rotational (side-drive with rotor poles and harmonic side-drive) microactuators.<<ETX>>

A micromachined RF microswitch applicable to phased-array antennas

A mechanical microswitch has been fabricated by single crystal silicon bulk micromachining on a glass substrate. The mechanical part of the device has superior mechanical reliability and can be applied to a phased-array antenna, since the glass substrate can be easily extended to a large area, accommodating a large number of elements on it. A fabricated device was measured to have less than 0.2 dB of on-state insertion loss and higher than 13 dB of off-state isolation at 30 GHz.

High-density tactile sensor arrays

In this paper, several different approaches for high-density tactile sensor arrays are first briefly examined. Among them, a silicon micromachined tactile imager approach is very attractive through achieving high density and good reproducibility, and can be mass produced. Therefore, silicon tactile imagers, including the results of very recent research efforts, are described in detail in this paper.

Hemispherical-grained LPCVD-polysilicon films for use in MEMS applications

Hemispherical-grained (HSG) polysilicon was shown to have tensile stress built in an as-deposited layer and considerable surface roughness. These features are very different from those of conventional polysilicon and amorphous silicon, while HSG can be fabricated in a manner similar to conventional LPCVD. This is related to the fact that the formation of HSG occurs on the amorphous surface, while polycrystallization due to annealing usually occurs at the silicon-to-silicon-dioxide interface. These intrinsic characteristics of HSG are applicable to Micro Electro Mechanical Systems (MEMS) for fabricating a wide variety of freestanding structures by preventing these flexible structures from being stuck to other more rigid structures.

Process alternatives and scaling limits for high-density silicon tactile imagers

Abstract In this paper the process complexities and parasitic substrate coupling effects are compared for several different high-density capacitive tactile imagers. The dissolved-wafer process using diffused bulk-silicon row lines and metal-on-glass columns is found to offer the simplest process and fastest response, requiring only five non-critical masks and producing a settling time for the column charge of about 1 μs. Using this process, a 1024-element array with a force range of 1 gm and a spatial resolution of 500 μm produces a force resolution equivalent to seven bits. Scaled to a 4096-element array, this same process should produce a force resolution of nearly six bits for the same force range and a spatial resolution of 250 μm.

Nonlinear analyses on CMOS integrated silicon pressure sensor

This paper reports theoretical and experimental results of analysis on nonlinear characteristics, for the newly designed CMOS integrated pressure sensor with square silicon diaphragm. It is shown that nonlinearity is caused by both the large diaphragm deflection effect and nonlinear piezoresistance effect of resistors. The optimum layout for piezoresistors to minimize their nonlinearity is also shown. The measured nonlinearity for the fabricated device quantitatively agrees well with the numerically analyzed nonlinearity.

Fabrication of NIST-format x-ray masks with 4-Gb DRAM patterns

We fabricated NIST-format x-ray masks containing test patterns for the gate and contact-hole (C/H) levels of 4- Gbit dynamic random access memory (DRAM), and evaluated the image placement (IP) accuracy, critical dimension (CD) control, and other characteristics. Due to precise control of the stress in the TaBN absorber and CrN films and also the high stiffness of the 3micrometers -thick SiC membrane, the reproducibility of the process-induced distortion was better than 10nm. Using the high-precision EB-X3 electron beam (EB) mask writer, the best IP accuracy obtained for a finished gate-level mask was 15nm (3(sigma) ) and its CD uniformity was +/- 6nm in a 24-mm-sq field. The relative IP accuracy of the C/H-level mask with respect to the gate- level mask was 11 nm (3(sigma) ) after magnification correction. These masks are useful for exposure using a 10micrometers gap because the mask surface is convex and the out- of0plane distortion of the membrane is less than 1micrometers . The optical transmittance of the SiC membrane is large enough for the alignment system of the XRA x-ray stepper. The specifications of a 100-nm-node x-ray mask can be met by using the EB-X3 and a TaBN/CrN/SiC/Si/Pyrex x-ray mask structure.