Kenneth Brakeley Welles

Delay hopped transmitted reference experimental results

This paper describes the experimental hardware design and implementation for a delay hopped transmitted reference communication system. The hardware is designed to generate the delay hopped transmitted reference signal for a number of experimental conditions. It can be used either in an ultra wideband pulse mode, ultra wideband noise mode, or in a narrowband mode. We use the experimental hardware setup to conduct link experiments with a delay hopped transmitted reference communication system. Experiments were conducted in an indoor multipath environment to test the viability of delay hopped transmitted reference for short-range indoor communications. The experimental results presented demonstrate that this modulation format is capable of transmitting data short range indoors without line of sight transmission path with minimal transmitted RF power.

Recursive computation of the Fourier transform

Efficient recursive methods and circuits for computing a continuously updated discrete Fourier transform (DFT) of an input-digital signal are considered. The Fourier transform (FT) is recomputed at each sample input time, with only O(N) operations being required to compute the transform, where N is the number of frequency bins. Various window functions are considered for windowing the input-wave form, namely a rectangular window, a triangular window, and an exponential window. The last type of window has not been widely considered in the past, partly due to its asymmetrical shape, and hence nonlinear phase response. Nevertheless, it is shown to have certain advantages in ease of computation and in flexibility. For the exponential window, a circuit that conveniently allows zooming in to particularly interesting parts of the frequency spectrum is shown. By appropriately loading a multiplier storage RAM, arbitrarily fine resolution may be achieved in any part of the spectrum, thus permitting closely adjacent peaks to be distinguished. The general approach is based on the interpretation of the FT as a set of simultaneous bandpass filters. Though these filters are generally finite-impulse-response filters, computational advantages are derived from formulating them as recursive filters.<<ETX>>

A 36-chip multiprocessor multichip module made with the General Electric high density interconnect technology

A unique packaging and interconnect technology was used to build a multichip, four-CPU-element, pipeline parallel processing computer module using Texas Instruments TMS320C25 digital signal processors and companion circuits. The technology allowed a greater than fifteen-fold reduction in area over conventional chip packages mounted with printed circuit board methods. Reduced interconnect capacitance coupled with elimination of conventional package parasitics allowed clocking of commercial 40 MHz parts to nearly 90 MHz.<<ETX>>

A high-speed, high-density multiprocessing module made with the general electric high-density interconnect technology

Digital signal processing technology has developed to the point that conventional chip packaging and circuit board technologies are limiting system performance. Recent advances in Multichip Module (MCM) technology from several sources permit a higher performance and a more dense alternative for constructing DSP-based circuits. GE has developed one of the most space efficient and highest performance MCM fabrication processes. This process was used to build a multichip, four-CPU-element, pipeline parallel processing computer module. Off-the-shelf DSP chips (Texas Instruments TMS320C25), static RAM, dual-ported RAM, and logic chips were used. This multichip digital signal processor with module design and fabrication has been supported by Defense Advanced Research Projects Agency (DARPA). Circuit size was reduced 15-fold over conventional chip packages and printed circuit board methods. An additional benefit of this technology, reduced interconnect capacitance coupled with elimination of conventional package parasitics, allowed doubling of the commercial 40-MHz clock rate to more than 80 MHz.

A rapid-prototyping environment for digital-signal processors

A description is given of the Diodes system, a complete rapid prototyping, debugging, and test environment including both hardware and software, for the design of digital-signal-processing chips. The test circuitry in Diodes differs from that in many systems, including those based on boundary scan, by offering full-speed circuit testing and the observation of internal nodes during real time. Diodes also achieves nearly 100% fault coverage because chips are composed of numerous chunks, each of which is tested exhaustively. The discussion covers the high-density interconnection technology and the concepts on which Diodes is based, two types of chips that have been designed, fabricated, and tested for Diodes: module assembly and fabrication; synthesis software; on-chip testing; Diodes test circuitry; test modes; and hardware and software debugging. Diodes is compared with other testing approaches and other rapid prototyping systems.<<ETX>>

A synthesis, test and debug environment for rapid prototyping of DSP designs

Recently, considerable progress has been made in the design of digital signal processing (DSP) integrated circuits and systems. In order to address the need for rapid and economical production and testing of hardware prototypes, a hardware and software system called DIODES is being developed for the rapid prototyping, testing and debugging of DSP designs. DIODES will allow the user to design a DSP system, have it partitioned into predefined function blocks, have it assembled using advanced packing technology and then thoroughly test and debug the design both stand-alone and in a larger electronic system environment. This paper gives an overview of the whole system focussing particularly on the debugging hardware and software support environment. The algorithmic description is translated by the DIODES synthesis software into a structural specification suitable for High-Density Interconnect (HDI) fabrication. The synthesis process includes the insertion of test capabilities into the hardware to allow for debugging the design. The rapid turnaround of HDI fabrication means that the user can have a prototype DIODES module in hand ready for testing within at most a day or two, and at moderate cost.<<ETX>>

Rapid prototyping of electronic systems

Describes a system for the rapid prototyping, testing and debugging of DSP designs. The DSP algorithm is first coded in a high level algorithmic language. This description is translated by the synthesis software into a structural specification suitable for HDI fabrication. The synthesis process includes the insertion of test capabilities into the hardware to allow for debugging the design. The rapid turnaround of HDI fabrication means that the user can have a prototype HDI module (DSP accelerator) in his hands ready for testing within at most a day or two, and at moderate cost. The DSP accelerator is then placed in a socket on a specially designed board (called the mother-board), connected to a Sun or other workstation, where it may be thoroughly tested and debugged. The debugging capabilities include structural verification, debugging and in-system test. Structural verification is testing the DSP accelerator to see that it is connected together correctly and that all the parts are working. Debugging involves sending test vectors through the chip, stepping, observing internal node values and limited reconfigurability with the purpose of debugging the algorithm. In-system test is done by connecting the DSP accelerator via a cable into the target system. This allows the system to be run at full speed (up to 20 MHz) with the DSP accelerator in place, but still retaining full observability of internal nodes.<<ETX>>

A testing methodology for large scale hybrid VLSI

A test methodology for large systems-on-a-chip designed by the Discretionary Interconnect One Day Electronic System (DIODES) system for the rapid prototyping of digital signal processing (DSP) electronic systems is discussed. DIODES is based on the concept of building a library of chips that implement a set of operators used in DSP algorithms, and using these chips to implement DSP algorithms by implanting them on an alumina substrate and interconnecting them appropriately to realize the desired functionality. Test hardware capabilities are discussed. A description of test circuitry is given. The test methodology is compared with boundary scan.<<ETX>>