Kenny Johansson

A detailed complexity model for multiple constant multiplication and an algorithm to minimize the complexity

Multiple constant multiplication (MCM) has been an active research area for the last decade. Most work so far have only considered the number of additions to realize a number of constant multiplications with the same input. In this work, we consider the number of full and half adder cells required to realize those additions, and a novel complexity measure is proposed. The proposed complexity measure can be utilized for all types of constant operations based on shifts, additions and subtractions. Based on the proposed complexity measure a novel MCM algorithm is presented. Simulations show that compared with previous algorithms, the proposed MCM algorithm have a similar number of additions while the number of full adder cells are significantly reduced.

Bit-Level Optimization of Shift-and-Add Based FIR Filters

Implementation of FIR filters using shift-and-add multipliers has been an active research area for the last decade. However, almost all algorithms so far has been focused on reducing the number of adders and subtractors, while little effort was put on the bit-level implementation. In this work we propose a method to optimize the number of full adders and half adders required to realize a given number of additions. We present results which show that both area and power consumption can be reduced using the proposed method.

Implementation of elementary functions for logarithmic number systems

Computations in logarithmic number systems require realisations of four different elementary functions. In the current paper the authors use a recently proposed approximation method based on weighted sums of bit-products to realise these functions. It is shown that the considered method can be used to efficiently realise the different functions. Furthermore, a transformation is proposed to improve the results for functions with logarithmic characteristics. Implementation results shows that significant savings in area and power can be obtained using optimisation techniques.

Adjustable Fractional-Delay FIR Filters Using the Farrow Structure and Multirate Techniques

The Farrow structure can be used for efficient realization of adjustable fractional-delay finite-length impulse response (FIR) filters, but, nevertheless, its implementation complexity grows rapidly as the bandwidth approaches the full bandwidth. To reduce the complexity, a multirate approach can be used. In this approach, the input signal is first interpolated by a factor of two via the use of a fixed half-band linear-phase FIR filter. Then, the actual fractional-delay filtering takes place. Finally, the so generated signal is downsampled to retain the original input/output sampling rate. In this way, the bandwidth of the fractional-delay filter used is halved compared to the overall bandwidth. Because the complexity of half-band linear-phase FIR filter interpolators is low, the overall complexity can be reduced. In this paper, we present more implementation details, design trade-offs, and comparisons when the filters are implemented using multiple constant multiplication techniques, which realize a number of constant multiplications with a minimum number of adders and subtracters

Minimum adder depth multiple constant multiplication algorithm for low power FIR filters

In this work we propose a graph based minimum adder depth algorithm for the multiple constant multiplication (MCM) problem. Hence, all multiplier coefficients are here guaranteed to be realized at the theoretically lowest depth possible. The motivation for low adder depth is that this has been shown to be a main factor for the power consumption. An FIR filter is implemented using different MCM algorithms, and the proposed algorithm result in 25% lower power in the MCM part compared to algorithms focused on minimizing the number of adders.

Algorithm to reduce the number of shifts and additions in multiplier blocks using serial arithmetic

In this paper an algorithm for realization of multiplier blocks using bitand digit-serial arithmetic is presented. Previously presented algorithms were designed for bit-parallel arithmetic and for that reason assumed no cost for shifts. It is shown that the new algorithm reduces the total complexity significantly.

Implementation of Polyphase Decomposed FIR Filters for Interpolation and Decimation Using Multiple Constant Multiplication Techniques

Multiple constant multiplication (MCM), i.e., realizing a number of constant multiplications using a minimum number of adders and subtracters, has been an active research area for the last decade. Almost all work has been focused on single rate FIR filters. However, for polyphase interpolation and decimation FIR filters there are two different implementation alternatives. For interpolation, direct form subfilters lead to fewer registers as they can be shared among the subfilters. The arithmetic part corresponds to a matrix vector multiplication. Using transposed direct form subfilters, the registers can not be shared, while the arithmetic part has the same input to all coefficients, and, hence, the redundancy between the coefficients is expected to be higher. For decimation filters the opposite holds for direct form and transposed direct form subfilters. In this work we discuss the trade-off between adders/subtracters and registers, and present implementation results for area, speed, and power for different realizations

Power Estimation for Ripple-Carry Adders with Correlated Input Data

In this work modelling of the power consumption for ripple-carry adders implemented in CMOS is considered. Based on the switching activity of each input bit, two switching models, one full and one simplified, are derived. These switching models can be used to derive the average energy consumed for one computation. This work extends previous results by introducing a data dependent power model, i.e., correlated input data is considered. Examples show that the switching model is accurate, while there are some differences in the power consumption. This is due to the fact that not all switching in the ripple-carry adder is rail-to-rail (full swing) in the actual implementation.

Approximation of elementary functions using a weighted sum of bit-products

In this work a novel approach for approximating elementary functions is presented. By rewriting the function as a sum of weighted bit-products an efficient implementation is obtained. For most functions a majority of the bit-products can be neglected and still obtain good accuracy. The method is suitable for high-speed implementation of fixed-point functions

Efficient sine and cosine computation using a weighted sum of bit-products

An angle rotation based approach to simultaneously compute sin(x) and cos(x) is presented. The approach yields a weighted sum of bit-products of the binary bits that represent the angle x. We discuss the required number of terms in the polynomial as well as the required coefficient wordlength as function of accuracy. The approach yields a combinatorial realization with a low complexity. We also propose a corresponding fast and simple architecture. The combinatorial circuit has low latency and can easily be pipelined for a high throughput.