Kensuke Shimizu

Residue arithmetic circuits using a signed-digit number representation

A new concept on residue arithmetic using a radix-2 signed-digit (SD) number representation is presented, by which memoryless residue arithmetic circuits using SD adders can be implemented. For a given modulus m, 2/sup p/-1/spl les/m/spl les/2/sup p/+2/sup p-1/-1, in a residue number system (RNS), the modulo m addition is performed by using two p-digit SD adders. Thus, the module m addition time is independent of the word length of operands. When m=2/sup p/ or m=2/sup p//spl plusmn/1, especially, the module m addition is implemented by only using one SD adder. Moreover, a module m multiplier can be constructed using a binary modulo m SD adder tree, so that the modulo m multiplication can be performed in a time proportional to log/sub 2/p.

Algorithm for generating a digital circle on a triangulargrid

An algorithm for determining the node-to-node movements to generate a digital circle on atriangular grid is given. At each step, we choose the one of three directions which minimizes |f(u, v)| where f(u,v)=0 is the circle equation.

Fast residue arithmetic multipliers based on signed-digit number system

Fast residue arithmetic multipliers based on a radix-2 signed-digit (SD) number are presented. For a given modulus m, 2/sup p/-1/spl les/m/spl les/ 2/sup p/+2/sup p-1/-1, in a residue number system (RNS), the modulo m addition is performed by using one or two p-digit SD adders, and the modulo m addition time is independent of the word length of operands. We propose two kinds of modulo m multipliers which are constructed using a modulo m SD adder and a binary tree of the adders and the modulo m multiplication are performed in a time proportional to p and log/sub 2/p, respectively. 16-digit residue arithmetic multiplier circuits have been designed using VHDL, and the results show that high speed residue arithmetic circuits can be implemented.

Residue arithmetic multiplier based on the radix-4 signed-digit multiple-valued arithmetic circuits

Residue arithmetic multiplier based on the radix-4 signed-digit arithmetic is presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, two radix-4 signed-digit (SD) number representations, (-2,-1,0,1,2) and (-3,-2,-1,0,1,2,3), are introduced. The former is used for the input and output, and the latter for the inner arithmetic circuit of the presented multiplier. So that, by using integers 4/sup P/ and 4/sup P//spl plusmn/1 as moduli of residue number system (RNS), where p is a positive integer, both the partial product generating circuit and the circuit for sum of the partial products in the multiplier can be efficiently constructed based on the SD number representations. The module m addition, m=4/sup P/ or m=4/sup P//spl plusmn/1, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time is independent of the word length of operands. The modulo m multiplier can be compactly constructed using a binary modulo m SD adder tree based on the multiple-valued addition circuits, and consequently the module m multiplication is performed in O(log/sub 2/p) time.

Pseudocube-based expressions to enhance testability

Sum-of-Pseudoproduct (SPP) forms are new logic representations and have made it possible to represent Boolean functions with more smaller expression than standard Sum-of-Products (SOP) forms. Our experimental results show that SPP forms require many fewer products and literals than SOP and ESOP for practical networks. Moreover, we show that SPP forms are more testable than ESOP forms. Next, we propose EXOR-Sum-of-Pseudoproduct (ESPP) form. This form is an EXOR-AND-EXOR one and enhances the random pattern testability. Experimental results show that ESPP forms are more testable than SPP and ESOP. Furthermore, they have the new possibility of compactness of the networks. We derive an upper bound on the number of pseudo-products to realize an arbitrary n-variable function by ESPP form.

Fast modular multiplication using Booth recoding based on signed-digit number arithmetic

Proposes a new algorithm of serial modular multiplication based on signed-digit (SD) number system using Booth recoding method. By introducing a p-digit radix-two SD number system, a modular addition is easily implemented by using one or two SD adders, so that no carry propagation will arise during the additions. A modular multiplication can be performed by repeating the modular addition with modular partial products. In order to implement a high speed modular multiplication, a Booth recoding method is used to reduce the partial products to be added for the modular multiplication. We also give a pipeline architecture with two modular SD adders to realize a faster modular multiplication. The design result by using VHDL shows that a fast modular multiplier can be implemented based on the presented method.

Error detection of arithmetic circuits using a residue checker with signed-digit number system

An error detection method for arithmetic circuits is proposed, by using a residue checker which consists of a number of residue arithmetic circuits designed based on radix-2 signed-digit (SD) number arithmetic. Fast modulo m(m=2/sup p//spl plusmn/1) multipliers and binary-to-residue number converters are constructed with a binary tree structure of modulo m SD adders. The modulo m addition is implemented by using a p-digit SD adder, so that the modulo m addition time is independent of the word length of operands. Therefore, the modulo m multiplication is performed in a time proportional to log/sub 2/p and an n-bit binary number is converted into a p-digit SD residue number in a time proportional to log/sub 2/(n/p). The presented residue arithmetic circuits can be applied to error detection for a large product-sum circuit.

Residue arithmetic circuits based on the signed-digit multiple-valued arithmetic circuits

Multiple-valued residue arithmetic circuits using integers 4/sup p/ and 4/sup p//spl plusmn/1 as moduli of residue number system (RNS) are presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, a radix-4 signed-digit (SD) number system is introduced, and the compact SD adder based on the multiple-valued current-mode circuits is applied for the implementation of high-speed and compact residue arithmetic circuits. The modulo m addition, m=4/sup p/ or m=4/sup p//spl plusmn/1, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time was independent of the word length of operands. Modulo m multiplier can be compactly constructed using a binary modulo m SD adder tree based on the multiple-valued addition circuits, and the modulo m multiplication can be performed in a time proportional to log/sub 2/p.

A new RNS to mixed-radix number converter using modulo (2/sup p/ - 1) signed-digit arithmetic

In this paper, a hardware algorithm converting the numbers in a residue number system (RNS) to that in a mixed-radix number system by using signed-digit (SD) arithmetic is presented. In each residue digit of the RNS, integers mi = (2Pi - 1) are used as the moduli and the modulo m addition and multiplication can be performed by an end-around-carry SD adder and a binary modulo m SD adder tree, respectively. Thus a high speed converter can be designed by using the proposed modulo m SD adders and multipliers

Modulo (2/sup p/ /spl plusmn/ 1) multipliers using a three-operand modular addition and Booth recoding based on signed-digit number arithmetic

A new three-operand modulo (2/sup p/ /spl plusmn/ 1) addition is presented, performing a carry-save addition and a two-operand modular addition based on the p-digit radix-two signed-digit (SD) number system. When a modulo (2/sup p/ /spl plusmn/ 1) multiplier is constructed as a ternary tree structure with the three-operand modular adders, the modular multiplication time is proportional to log/sub 3/p. When a serial modular multiplier is constructed, we give two architectures using the two-operand and three-operand modular adders, respectively. A Booth recoding method is also proposed to reduce the modular partial products. The design and simulation results by VHDL show that high speed modular multipliers can be obtained by the presented algorithms.