Yasuaki Nishitani

The firing squad synchronization problem for graphs

Abstract In this paper, we give a solution of the Firing Squad Synchronization Problem for graphs. The synchronization times of solutions which have been obtained are proportional to the number of nodes of a graph. The synchronization time of our solution is proportional to the radius rG of a graph (G (3rG + 1 or 3rG time units, where rG, is the longest distance between the general and any other node of G. This synchronization time is minimum for an infinite number of graphs.

On universality of concurrent expressions with synchronization primitives

Abstract Concurrent expressions are a class of extended regular expressions with a shuffle operator (‖) and its closure ( ). The class of concurrent expressions with synchronization primitives, called synchronized concurrent expressions, is introduced as an extended model of Shaws flow expressions. This paper discusses some formal properties of synchronized concurrent expressions from a formal language theoretic point of view. It is shown that synchronized concurrent expressions with three signal/wait operations are universal in the sense that they can simulate any semaphore controlled concurrent expressions and they can describe the class of recursively enumerable sets. Some results on semaphore controlled regular expressions are also included to give a taste of more positive results.

EXACT MINIMIZATION OF AND–EXOR EXPRESSIONS OF PRACTICAL BENCHMARK FUNCTIONS

We propose faster-computing methods for the minimization algorithm of AND–EXOR expressions, or exclusive-or sum-of-products expressions (ESOPs), and obtain the exact minimum ESOPs of benchmark functions. These methods improve the search procedure for ESOPs, which is the most time-consuming part of the original algorithm. For faster computation, the search space for ESOPs is reduced by checking the upper and lower bounds on the size of ESOPs. Experimental results to demonstrate the effectiveness of these methods are presented. The exact minimum ESOPs of many practical benchmark functions have been revealed by this improved algorithm.

SPEEDUP OF THE n-PROCESS MUTUAL EXCLUSION ALGORITHM

We propose two modifications of the n-process mutual exclusion algorithm by Peterson for the asynchronous multi-writer/reader shared memory model. By any of the modifications we can speed up the original n-process algorithm. The running times for the trying regions of the first modified algorithm and the second modified algorithm are (2n - 3)c + O(n3 l) and (n - 1)c + O(n3 l), respectively, where n is the number of processes, l is an upper bound on the time between two steps, and c is an upper bound on the time that any user spends in the critical region. These running times are improvements on the running time, O(n2c + n4 l) of the original n-process algorithm for the same asynchronous shared memory model.

A faster algorithm of minimizing AND-EXOR expressions

We propose a faster algorithm of minimizing AND-EXOR expressions. While it has been considered difficult to obtain the minimum AND-EXOR expression of a given function with six variables in a practical computing time, our algorithm can compute the minimum AND-EXOR expressions of any six-variable and some seven-variable functions practically. In this paper, we first present a naive algorithm that searches the space of expansions of a given n-variable function f for a minimum expression of f. The space of expansions are generated by using all combinations of (n-1)-variable product terms. Then, how to prune the branches in the search process and how to restrict the search space to obtain the minimum solutions are discussed as the key point of reduction of the computing time. Finally, a faster algorithm is constructed by using the methods discussed. Experimental results to demonstrate the effectiveness of these methods are also presented.

Quantum Cost Reduction of Reversible Circuits Using New Toffoli Decomposition Techniques

Quantum cost is the most important criteria to evaluate reversible and quantum circuits. Also the fundamental building blocks of reversible and quantum circuits are Multiple-Control Toffoli (MCT) gates. The synthesis of MCT based reversible circuits are usually conducted into two steps. First, MCT circuits are decomposed into quantum circuits and then they are optimized using various techniques such as template matching, moving rules to reduce the quantum cost of reversible circuits. In this paper, we propose new techniques to decompose the Toffoli gates, in which MCT based circuits are mapped into a corresponding quantum realization. The main improvement is that the resulting quantum realization of MCT based circuits makes significantly better realization than those achieved in the earlier approaches and further reduction is possible using some other optimization techniques. Experimental results show that our new techniques enable to get sub-optimal realization of the MCT based reversible circuits in decomposition stage and quantum cost reduction of the reversible circuits is achieved by using that sub-optimal realization.

Efficient search methods for obtaining exact minimum AND-EXOR expressions

We propose three search methods for obtaining exact minimum AND-EXOR expressions: the depth-first, the breadth-first, and the depth-first-when-optimum searches. They minimize up to 7-variable functions in a practical computation time. Experimental results to compare the efficiency of these methods are presented. The depth-first search, which saves the memory consumption, minimizes the 16-variable benchmark function t481 without memory exhaustion. This search method is the fastest among these three methods on the average computation time for randomly-generated single-output functions. The depth-first-when-optimum search is the fastest on the computation time for the most of benchmark functions. For some benchmark functions, however, the breadth-first search is the fastest

Speedup of lockout-free mutual exclusion algorithms

We propose three lockout-free mutual exclusion algorithms for the asynchronous multi-writer/reader shared memory model. The first two algorithms are modifications of the n-process algorithm by G.L. Peterson (1981), and the third algorithm is a modification of the tournament algorithm by G.L. Peterson and M.J. Fischer (1977). The correctness and efficiency of these modified algorithms are shown. By these modifications we can speed up the original algorithms. The running times for the trying regions of the first algorithm and the second algorithm are (2n-3)c+O(n/sup 3/l) and (n-1)c+O(n/sup 3/l), respectively, where n is the number of processes, l is an upper bound on the time between successive two steps, and c is an upper bound on the time that any user spends in the critical region. The running time for the trying region of the third algorithm is (n-1)c+O(nl).

Easily testable realization based on OR-AND-EXOR expansion with single rail inputs

It is known that AND-EXOR two-level networks obtained by AND-EXOR expansion with positive literals are easily testable. They are based on the single-rail-input logic, and require (n+4) tests to detect their single stuck-at faults, where n is the number of the input variables. We present three-level networks obtained from the single-rail-input OR-AND-EXOR expansion and propose a more easily testable realization than the AND-EXOR networks. The realization is an OR-AND-EXOR network which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant (1/spl les/r/spl les/n). We show that only (r+n/r) tests are required to detect all the single stuck-at faults by adding r extra variables to the network.

Embeddings of Hyper-Rings in Hypercubes

A graph G=(V, E) with N nodes is called an N-hyper-ring if V={0,..., N−1} and E={(u, v) ¦ (u− v) modulo N is a power of 2}. We study embeddings of the 2n-hyper-ring in the n-dimensional hypercube. We show a greedy embedding with dilation 2 and congestion n+1 and a modified greedy embedding with dilation 4 and congestion 6.