Kensuke Takata

4-bit Bit-Slice Arithmetic Logic Unit for 32-bit RSFQ Microprocessors

A 4-bit bit-slice arithmetic logic unit (ALU) for 32-bit rapid single-flux-quantum microprocessors was demonstrated. The proposed ALU covers all of the ALU operations for the MIPS32 instruction set. It processes bit-sliced 32-bit data that are divided into eight slices of 4 bits. The bit-slice approach simplifies the circuit structure and reduces the hardware cost. The ALU uses synchronous concurrent-flow clocking and consists of eight pipeline stages. It was implemented using the 1.0-μm Nb/AlOx/Nb nine-layer advanced process 2 (ADP2) with a critical current density of 10 kA/cm2, and fabricated by National Institute of Advanced Industrial Science and Technology (AIST). It consists of 3481 Josephson junctions with an area of 3.09 × 1.66 mm2. It achieved the target frequency of 50 GHz and a latency of 524 ps for a 32-bit operation, at the designed DC bias voltage of 2.5 mV, via precise control of interconnect delays and clock distribution. Furthermore, it achieved a throughput of 6.25 × 109 32-bit operations per second. All the correct ALU operations with measured DC bias voltage margins of around 10% at 50 GHz were successfully obtained. The proposed ALU can be used for any 4n-bit processing.

Development of Bit-Serial RSFQ Microprocessors Integrated with Shift-Register-Based Random Access Memories

We report recent progress in the development of rapid single-flux-quantum (RSFQ) microprocessors integrated with random access memories (RAMs) based on bit-serial processing, called CORE e series. The bit-serial processing is an efficient, unique approach for RSFQ microprocessors that target ultrafast clock frequency with small hardware size. The CORE e series have a richer instruction set and RAMs integrated on the same die, and are capable of running small-scale benchmark programs. We are currently developing three microprocessors in parallel, CORE e2, e3, and e4, for different purposes including prototype demonstration, investigation on efficient use of hardware and energy, and full-function implementation. Here we describe design and implementation of the CORE e microprocessors together with a high-density shift-register-based RAM. The estimated performance of these microprocessors is 333 million instructions per second (MIPS) with 4.6-5.6 mW power.

Low-Voltage Bit-Serial Single-Flux-Quantum Microprocessor for Integrating Memories

We report an energy-efficient bit-serial microprocessor based on single-flux-quantum (SFQ) logic, called CORE e3, using a low-voltage bias technique. This microprocessor was designed for integrating memories, and we developed it to investigate the efficient use of hardware and energy, using the low-voltage rapid single-flux-quantum (LV-RSFQ) technique. We implemented the CORE e3 and its test circuit using a 10-kA/cm2 Nb process. We confirmed via logic simulations that all instructions were executed correctly with a 1-GHz system clock. We expect a 3.51 fold improvement in energy efficiency.

Sub-Milliwatt, 30-GHz Microprocessor Based on Low-Voltage Rapid Single-Flux-Quantum Circuit Technology

We report high-speed operation of low-power microprocessor prototype based on the low-voltage rapid single-flux-quantum (LV-RSFQ) circuit technology using superconductor devices. When a supply voltage is lowered, both static and dynamic energy consumption in RSFQ circuits are reduced, in exchange for slower switching speed. We optimized the supply voltage for most energy-efficient operation, and improved the energy-delay product (EDP) to one fifteenth of the previous design with the help of an advanced fabrication technology. The designed microprocessor operated at a clock frequency of 30 GHz with power consumption of 0.23 mW.