Hiroyuki Akaike

Fabrication process of planarized multi-layer Nb integrated circuits

To improve the operating speed and density of Nb single-flux-quantum integrated circuits, we developed an advanced fabrication process based on NECs standard process. We fabricated planarized six-Nb-layer circuit structures using this advanced process. This new structure has four Nb wiring layers for greater design flexibility. To shield the magnetic field produced by the DC bias current, the DC bias power supply layer was placed under the groundplane. The critical current density of the Josephson junction was 10 kA/cm/sup 2/. We fabricated and tested more than 10 wafers and demonstrated that the six-layer circuits were successfully planarized. We also confirmed insulation between each Nb layer and the reliability of superconducting contacts. This planarization did not significantly degrade the junction characteristics. We measured small spreads in the critical current of less than 2%. These results demonstrated the effectiveness of this advanced process based on mechanical-polishing planarization.

Demonstration of a 120 GHz single-flux-quantum shift register circuit based on a 10 kA/cm^2 Nb process

Designs and test results for a single-flux-quantum (SFQ) eight-bit shift register circuit operating at frequencies above 100 GHz are described. The high-speed performance was realized by introducing a planarized 10 kA cm−2 Nb fabrication process as an advanced process and by adopting middle-damped junctions with McCumber parameters βc of 1.8–2.9 in the circuit. The middle-damped junctions were used to reduce the repulsion between SFQ pulses and to adjust the timing. The circuit was designed using a cell-based design method and was tested by constructing an on-chip test system with a ladder-type four-bit high-frequency clock generator. We confirmed its correct operations up to 120 GHz.

On-chip test of the shift register for high-end network switch based on cell-based design

We have demonstrated the high-speed operation up to 55 GHz with a bias margin of ±5.5% for a shift register based on the single-flux-quantum logic circuit. The shift register is employed in the rate transfer circuit in high-end network switches that are made up with the cell-based design technique. The on-chip test system was used for measuring the operation frequencies, and the test system itself was built by combining the cells to satisfy the boundary conditions between the test system and the circuit-under-test. As a result, the on-chip test system developed in this study has high flexibility.

Quasiparticle-mediated spin Hall effect in a superconductor

In some materials the competition between superconductivity and magnetism brings about a variety of unique phenomena such as the coexistence of superconductivity and magnetism in heavy-fermion superconductors or spin-triplet supercurrent in ferromagnetic Josephson junctions. Recent observations of spin-charge separation in a lateral spin valve with a superconductor evidence that these remarkable properties are applicable to spintronics, although there are still few works exploring this possibility. Here, we report the experimental observation of the quasiparticle-mediated spin Hall effect in a superconductor, NbN. This compound exhibits the inverse spin Hall (ISH) effect even below the superconducting transition temperature. Surprisingly, the ISH signal increases by more than 2,000 times compared with that in the normal state with a decrease of the injected spin current. The effect disappears when the distance between the voltage probes becomes larger than the charge imbalance length, corroborating that the huge ISH signals measured are mediated by quasiparticles.

Planarized multi-layer fabrication technology for LTS large-scale SFQ circuits

We have been developing a 10 kA cm−2 Nb advanced fabrication process to make larger scale and higher speed SFQ circuits that have over 100k junctions. The main challenges in implementing this process are related to increasing the critical current density of junctions, decreasing design rules and increasing the number of Nb layers. We have proposed a planarized multi-layer structure, which consists of a Nb/AlOx/Nb junction layer, Nb wiring layers, Nb shield layers, a Nb layer for dc power, a Nb ground plane, SiO2 insulator layers and a Mo resistor layer. In fabricating this multi-layer structure, we have developed a new planarization technology which enables the flattening of the SiO2 insulator surface over the Nb wiring layer independent of the pattern sizes of the Nb wirings. This planarization technology consists of SiO2 bias sputtering, reactive ion etching with a reversal mask of the Nb wiring and mechanical polishing planarization. The SEM photographs showed excellent flatness for the planarized multi-layer structure.

Planarization Process for Fabricating Multi-Layer Nb Integrated Circuits Incorporating Top Active Layer

We have developed an advanced process for fabricating a next-generation multi-layer Nb integrated circuit structure incorporating a top active layer. In this structure, the passive-transmission-line (PTL) layer is placed between the top active layer and a DC-bias current layer at the bottom. This structure will make it possible to flexibly design active circuits and PTL wiring, and will also enable active circuits to be effectively shielded from magnetic fields generated by a large DC-bias current. Both the DC-bias current layer and the PTL layer are planarized; however, the top active layer is fabricated without planarization. To fabricate this new structure, it was necessary to achieve a better planarization process for junctions formed over underlying Nb patterns. The combined process we developed comprising additional SiO2 deposition and additional mechanical polishing after the standard Caldera planarization process results in superior planarization for junction formation. We obtained excellent characteristics of junctions formed over underlying pattern edges when they were fabricated on surfaces planarized using this new process. Using the process, we fabricated new 10-Nb-layer integrated circuit structures and estimated the characteristics of their circuit elements.

An Operand Routing Network for an SFQ Reconfigurable Data-Paths Processor

We report the progress in the development of an operand routing network (ORN) for an SFQ reconfigurable data-paths processor (SFQ-RDP). The SFQ-RDP is implemented as a two-dimensional array of floating-point units (FPU), outputs of which can be connected to the inputs of one or more FPUs in the next row via ORN. We have considered two architectures of the ORN: one is based on NDRO switches and the other - on crossbar switches. The comparison shows that the crossbar-based ORN has better performance due to the regular pipelined structure. We have designed a crossbar switch with a multicasting function and a 1-to-2 ORN prototype for 2.5 kA/cm2 process. The circuits have been experimentally tested at the frequencies up to 36 GHz.

Single-Flux-Quantum Circuit Based Readout System for Detector Arrays by Using Time to Digital Conversion

We propose a single-flux-quantum (SFQ) based readout circuit for a transition edge sensor (TES) array for X-ray radiation detection. Utilization of SFQ circuits for this purpose enables large-scale integration of TESs due to very high speed processing ability of the received signals and using an already established integrated circuit design environment. We utilize the cooling time dependence of the TES on the incident X-ray energy. Time to digital conversion is made by using an SFQ based quasi-one-junction SQUID (QOS), which works as a 1-bit comparator with an adjustable current threshold level, and an SFQ based high speed counter. The readout system is composed of two separate chips that are connected to each other with flexible superconducting wiring. The QOS-multiplexer chip is directly connected to the TES array and it performs the digital conversion of the TES output. The demultiplexer-counter chip, which will be placed at elevated temperatures, receives the multiplexed SFQ pulses and determines the duration of the TES output which is above the predetermined threshold level. Final goal of this work is to readout more than 10 k TES pixels and in this paper, feasibility of the system and current status of the development process is demonstrated.

Dynamic fluctuations in the superconductivity of nbn films from microwave conductivity measurements

We have measured the frequency and temperature dependences of complex ac conductivity, \sigma(\omega)=\sigma_1(\omega)-i\sigma_2(\omega), of NbN films in zero magnetic field between 0.1 to 10 GHz using a microwave broadband technique. In the vicinity of superconducting critical temperature, Tc, both \sigma_1(\omega) and \sigma_2(\omega) showed a rapid increase in the low frequency limit owing to the fluctuation effect of superconductivity. For the films thinner than 300 nm, frequency and temperature dependences of fluctuation conductivity, \sigma(\omega,T), were successfully scaled onto one scaling function, which was consistent with the Aslamazov and Larkin model for two dimensional (2D) cases. For thicker films, \sigma(\omega,T) data could not be scaled, but indicated that the dimensional crossover from three dimensions (3D) to 2D occurred as the temperature approached Tc from above. This provides a good reference of ac fluctuation conductivity for more exotic superconductors of current interest.

Fabrication of submicron Nb/AlO/sub x/-Al/Nb tunnel junctions using focused ion beam implanted Nb patterning (FINP) technique

We have successfully fabricated 0.2 /spl mu/m/sup 2/ Nb/AlO/sub x//Nb tunnel junctions using the focused-ion-beam implanted Nb patterning (FINP) technique for junction definition. The success was due to improvement of the edge profile of the counter electrode. The vertical edge profile was realized with the large etching selectivity of Ga implanted Nb over unimplanted Nb by controlling the reactive neutrals in the plasma. The critical current I/sub c/ and the quality parameter V/sub m/ of 0.2 /spl mu/m/sup 2/ junctions were 10.5 /spl mu/A and 11 mV, respectively. The R/sub sg//R/sub n/ was 12. The maximum to minimum spread in I/sub c/ of 60 series junctions with areas of 0.5 /spl mu/m/sup 2/ was /spl plusmn/10%.<<ETX>>