Kent E. Wires

Combined IEEE compliant and truncated floating point multipliers for reduced power dissipation

Truncated multiplication can be used to significantly reduce power dissipation for applications that do not require correctly rounded results. This paper presents a power efficient method for designing floating point multipliers that can perform either correctly rounded IEEE compliant multiplication or truncated multiplication, based on an input control signal. Compared to conventional IEEE floating point multipliers, these multipliers require only a small amount of additional area and delay, yet provide a significant reduction in power dissipation for applications that do not require IEEE compliant results.

FPGA Resource Reduction Through Truncated Multiplication

Significant reductions in FPGA resources, delay, and power can be achieved using truncated multipliers instead of standard parallel multipliers when the full precision of the standard multiplier is not required. With truncated multiplication, the less significant columns of the multiplication matrix are eliminated and correction terms are added to keep the total error to less than one unit in the last place. The truncated multiplication techniques presented in this paper are applied to FPGA parallel multipliers, and can be used in conjunction with a number of other performance enhancing techniques, such as pipelining, Booth encoding, and device specific optimizations to increase the effectiveness of device mapping, placing, and routing.

Reciprocal and Reciprocal Square Root Units with Operand Modification and Multiplication

Abstract.Reciprocals and reciprocal square roots are used in several digital signal processing, multimedia, and scientific computing applications. This paper presents high-speed methods for computing reciprocals and reciprocal square roots. These methods use a table lookup, operand modification, and multiplication to obtain an initial approximation. This is followed by a modified Newton-Raphson iteration, which improves the accuracy of the initial approximation. The initial approximation and Newton-Raphson iteration employ specialized hardware to reduce the delay, area, and power dissipation. The application of these methods is illustrated through the design of reciprocal and reciprocal square root units for operands in the IEEE single precision format. These designs are pipelined to produce a new result every clock cycle.